We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
Custom Circuits Design Engineer
$150K - $277K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Custom Circuits Design Engineer
$150K - $277K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Custom Circuits Design Engineer
$150K - $277K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Custom Circuits Design Engineer
$150K - $277K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...
Analog and Mixed Signal Design Engineer
Hillsboro, OR · On-site
$164K - $269K/yr
... SRAM, RF, ROM, eDRAM, Fuse, etc.), Analog Circuit Reference Designs (PLL, BGR, ADC, etc.), High ... Work closely with process and IP engineers to anticipate AMS IP requirements and use design and ...
Analog and Mixed Signal Design Engineer
Hillsboro, OR · On-site
$164K - $269K/yr
... SRAM, RF, ROM, eDRAM, Fuse, etc.), Analog Circuit Reference Designs (PLL, BGR, ADC, etc.), High ... Work closely with process and IP engineers to anticipate AMS IP requirements and use design and ...
Design Engineer
$75K - $100K/yr
... for a Design Engineer. ESSENTIAL FUNCTIONS * May coordinate multiple small projects or large ... Associates Degree or Bachelor's Degree preferred, but not required. * High School Diploma or GED ...
Quick apply
Design Engineer
$75K - $100K/yr
... for a Design Engineer. ESSENTIAL FUNCTIONS * May coordinate multiple small projects or large ... Associates Degree or Bachelor's Degree preferred, but not required. * High School Diploma or GED ...
Analog and Mixed Signal Design Engineer
$164K - $269K/yr
... SRAM, RF, ROM, eDRAM, Fuse, etc.), Analog Circuit Reference Designs (PLL, BGR, ADC, etc.), High ... Work closely with process and IP engineers to anticipate AMS IP requirements and use design and ...
Analog and Mixed Signal Design Engineer
$164K - $269K/yr
... SRAM, RF, ROM, eDRAM, Fuse, etc.), Analog Circuit Reference Designs (PLL, BGR, ADC, etc.), High ... Work closely with process and IP engineers to anticipate AMS IP requirements and use design and ...
Mechanical Product Design Engineer I
Portland, OR · Hybrid
$71K - $91K/yr
Bachelor of Mechanical Engineering or related engineering degree, or a corresponding associates degree with 4 years related experience * Experience with CADD software. Experience in CADD design of ...
Mechanical Product Design Engineer I
Portland, OR · Hybrid
$71K - $91K/yr
Bachelor of Mechanical Engineering or related engineering degree, or a corresponding associates degree with 4 years related experience * Experience with CADD software. Experience in CADD design of ...
Apply now for our Wastewater Treatment Design/Process Engineer position. This opportunity is ... Keller Associates, Inc. is an Equal Opportunity Employer All qualified applicants will receive ...
Apply now for our Wastewater Treatment Design/Process Engineer position. This opportunity is ... Keller Associates, Inc. is an Equal Opportunity Employer All qualified applicants will receive ...
Apply now for our Wastewater Treatment Design/Process Engineer position. This opportunity is ... Keller Associates, Inc. is an Equal Opportunity Employer All qualified applicants will receive ...
Quick apply
Apply now for our Wastewater Treatment Design/Process Engineer position. This opportunity is ... Keller Associates, Inc. is an Equal Opportunity Employer All qualified applicants will receive ...
Apply now for our Water Treatment Design/Process Engineer position. This opportunity is also ... Keller Associates, Inc. is an Equal Opportunity Employer All qualified applicants will receive ...
Apply now for our Water Treatment Design/Process Engineer position. This opportunity is also ... Keller Associates, Inc. is an Equal Opportunity Employer All qualified applicants will receive ...
Associate Sram Design Engineer information
See Portland, OR salary details
$44K - $52.7K
1% of jobs
$52.7K - $61.5K
6% of jobs
$61.5K - $70.2K
17% of jobs
$70.3K is the 25th percentile. Wages below this are outliers.
$70.2K - $78.9K
22% of jobs
The median wage is $80.7K / yr.
$78.9K - $87.6K
18% of jobs
$87.6K - $96.4K
10% of jobs
$97.1K is the 75th percentile. Wages above this are outliers.
$96.4K - $105.1K
10% of jobs
$105.1K - $113.8K
8% of jobs
$113.8K - $122.5K
4% of jobs
$122.5K - $131.3K
2% of jobs
$131.3K - $140K
2% of jobs
$44K
$87.6K
$140K
How much do associate sram design engineer jobs pay per year?
As of Jul 31, 2026, the average yearly pay for associate sram design engineer in Portland, OR is $87,636.00, according to ZipRecruiter salary data. Most workers in this role earn between $69,500.00 and $100,700.00 per year, depending on experience, location, and employer.
What is the difference between Associate Sram Design Engineer vs Memory Design Engineer?
| Aspect | Associate Sram Design Engineer | Memory Design Engineer |
|---|---|---|
| Credentials | Bachelor's in Electrical Engineering or related field; some roles may prefer a Master's | Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related discipline |
| Work Environment | Design teams in semiconductor or electronics companies, focusing on SRAM architecture and circuit design | Memory development teams working on various types of memory, including SRAM, DRAM, and Flash |
| Industry Usage | Commonly used in semiconductor companies, consumer electronics, and hardware startups | Widely used across semiconductor, consumer electronics, and data storage industries |
While both roles involve memory technology and circuit design, an Associate Sram Design Engineer specializes specifically in SRAM architecture and design, whereas a Memory Design Engineer may work on a broader range of memory types. The Associate Sram Design Engineer typically focuses on SRAM-related projects within semiconductor companies, making it a more specialized position.
What are Associate SRAM Design Engineers?
Associate SRAM Design Engineers are entry-level professionals who work on the design, development, and verification of Static Random Access Memory (SRAM) circuits, which are crucial components in microprocessors and various digital devices. They assist senior engineers in tasks such as circuit schematic design, layout, simulation, and testing to ensure optimal performance, power efficiency, and reliability of SRAM blocks. Their role often involves working with electronic design automation (EDA) tools and collaborating with cross-functional teams to deliver robust memory solutions. This position is ideal for individuals with a background in electrical or electronics engineering and a strong understanding of digital circuit design principles.
What are the key skills and qualifications needed to thrive as an Associate SRAM Design Engineer, and why are they important?
To thrive as an Associate SRAM Design Engineer, you need a solid background in electrical engineering, CMOS circuit design, and semiconductor device physics, usually supported by a relevant degree. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), scripting languages, and possibly knowledge of Verilog or SPICE simulations is typically required. Strong problem-solving abilities, attention to detail, and effective teamwork are important soft skills in this role. These competencies are crucial to ensure accurate, reliable memory designs that meet performance, power, and area specifications in a collaborative engineering environment.
What are some common challenges an Associate SRAM Design Engineer may face when transitioning from academic projects to industry roles?
In transitioning from academia to an industry role as an Associate SRAM Design Engineer, you may encounter challenges such as adapting to strict project timelines, collaborating closely with cross-functional teams, and adhering to standardized design and verification flows. Unlike academic projects, industry work often requires balancing innovation with strict adherence to design specifications, power/performance constraints, and manufacturability. Additionally, you'll need to quickly become proficient with industry-standard EDA tools, scripting, and revision control systems, as well as participate in regular design reviews and debugging sessions with senior engineers.
What cities near Portland, OR are hiring for Associate Sram Design Engineer jobs? Cities near Portland, OR with the most Associate Sram Design Engineer job openings:
Apple rating
8.0
Based on 675 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Do you have a passion for crafting entirely new solutions? Do you love building without precedent? As part of our Digital group, you'll take imaginative and revolutionary ideas and determine how to turn them into reality. You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking, often literally. Join us, and you'll help design the tools that allow us to bring customers experiences they've never before envisioned. You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low power SOC.
Description
Imagine yourself at the center of our SOC design effort, collaborating with all fields, with a critical impact and playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of hardworking engineers. You will perform the following - - Develop custom circuits to improve chip power efficiency. - Work with power team, PD and architects to define specifications and requirements - Perform design, analysis, modeling/simulation, circuit level specifications, schematic capture, spice simulation / margin verification across PVT, statistical design, functional verification and silicon bring up.
- Work closely with layout team to complete the design and oversee the layout quality.
- Develop / drive circuit methodology to achieve the highest design quality metrics.
Minimum Qualifications
BS and a minimum of 3 years of relevant industry experience
Preferred Qualifications
We are looking for applicants with design experience in advanced technology nodes.
- Experience in design of low voltages / low power custom circuits.
- Experience in one or multiple of the following areas is highly desirable: Machine learning accelerators, SRAM circuits, non-volatile memories, weak / moderate inversion circuits, ultra-low power amplifiers, DC/DC converters, digital on-chip sensors, high speed clocking, time to digital converters (TDCs).
- Deep understanding of deep submicron device physics, leakage mechanisms, technology interactions with device behavior.
- Solid understanding of device matching, device noise sources (1/f, thermal), extrinsic noise sources (supply, jitter), and their impact on high precision circuit.
- Ability to conduct experiments during silicon debug, gathering and analyzing data; and utilize scripting to support efficient handling of ATE data.
- Familiar with mixed signal verification and behavioral models for mixed signal blocks.
- Proficiency in scripting languages (Python /Perl or others) and CAD automation tools.
- Knowledge of industry standard circuit and design tools.
Description
Imagine yourself at the center of our SOC design effort, collaborating with all fields, with a critical impact and playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of hardworking engineers. You will perform the following - - Develop custom circuits to improve chip power efficiency. - Work with power team, PD and architects to define specifications and requirements - Perform design, analysis, modeling/simulation, circuit level specifications, schematic capture, spice simulation / margin verification across PVT, statistical design, functional verification and silicon bring up.
- Work closely with layout team to complete the design and oversee the layout quality.
- Develop / drive circuit methodology to achieve the highest design quality metrics.
Minimum Qualifications
BS and a minimum of 3 years of relevant industry experience
Preferred Qualifications
We are looking for applicants with design experience in advanced technology nodes.
- Experience in design of low voltages / low power custom circuits.
- Experience in one or multiple of the following areas is highly desirable: Machine learning accelerators, SRAM circuits, non-volatile memories, weak / moderate inversion circuits, ultra-low power amplifiers, DC/DC converters, digital on-chip sensors, high speed clocking, time to digital converters (TDCs).
- Deep understanding of deep submicron device physics, leakage mechanisms, technology interactions with device behavior.
- Solid understanding of device matching, device noise sources (1/f, thermal), extrinsic noise sources (supply, jitter), and their impact on high precision circuit.
- Ability to conduct experiments during silicon debug, gathering and analyzing data; and utilize scripting to support efficient handling of ATE data.
- Familiar with mixed signal verification and behavioral models for mixed signal blocks.
- Proficiency in scripting languages (Python /Perl or others) and CAD automation tools.
- Knowledge of industry standard circuit and design tools.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976