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Assistant Digital Verification Engineer Jobs in California

Apple

Wireless Radio Verification Engineer

San Diego, CA

$122K - $214K/yr

As a Wireless Radio Verification Engineer, you'll ensure first-time-right silicon success through ... This role emphasizes digital verification while bridging to RF/analog domains-you'll work closely ...

Apple

Wireless Radio Verification Engineer

San Diego, CA

$122K - $214K/yr

As a Wireless Radio Verification Engineer, you'll ensure first-time-right silicon success through ... This role emphasizes digital verification while bridging to RF/analog domains-you'll work closely ...

Apple

Design Verification Engineer

Cupertino, CA · On-site

$167K - $204K/yr

Preferred Qualifications Skilled in many aspects of digital verification such as constrained random ... programming skills with knowledge of data structures and algorithms Experience with Python, Perl ...

Entrada Ventures

Verification Engineer

Palo Alto, CA · On-site

$160 - $220/hr

A Senior RTL Verification Engineer responsible for ensuring the functionality, correctness, and quality of complex digital designs across ASIC and FPGA platforms. This role focuses on building robust ...

Apple

Design Verification Engineer

Cupertino, CA · On-site

$167K - $204K/yr

Preferred Qualifications Skilled in many aspects of digital verification such as constrained random ... programming skills with knowledge of data structures and algorithms Experience with Python, Perl ...

Apple

Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Preferred Qualifications Skilled in many aspects of digital verification such as constrained random ... programming skills with knowledge of data structures and algorithms Experience with Python, Perl ...

Syntiant

Digital Design Engineer

San Diego, CA

$190K - $240K/yr

Verify the digital system and blocks in collaboration with the digital verification engineer. * Develop low-power audio signal processing architectures. Qualifications, Education, and Experience ...

Apple

Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Preferred Qualifications Skilled in many aspects of digital verification such as constrained random ... programming skills with knowledge of data structures and algorithms Experience with Python, Perl ...

Syntiant

Digital Design Engineer

San Diego, CA · On-site

$190K - $240K/yr

Verify the digital system and blocks in collaboration with the digital verification engineer. * Develop low-power audio signal processing architectures. Qualifications, Education, and Experience ...

Apple Inc.

Wireless Radio Verification Engineer

Sunnyvale, CA · On-site

$122.70 - $214.30/hr

As a Wireless Radio Verification Engineer, you'll ensure first-time-right silicon success through ... This role emphasizes digital verification while bridging to RF/analog domains--you'll work closely ...

Syntiant

Digital Design Engineer

San Diego, CA · On-site

$190K - $240K/yr

Verify the digital system and blocks in collaboration with the digital verification engineer. * Develop low-power audio signal processing architectures. Qualifications, Education, and Experience ...

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Assistant Digital Verification Engineer information

What does an assistant digital verification engineer do?

An Assistant Digital Verification Engineer supports the design and testing of digital circuits and systems to ensure they function correctly according to specifications. They assist in creating verification plans, writing and running simulations, debugging issues, and documenting results. Their work is essential in identifying design flaws early in the development process, which helps to improve the quality and reliability of electronic products. Typically, they work closely with design engineers and senior verification engineers as part of a larger hardware development team.

What are the key skills and qualifications needed to thrive as an assistant digital verification engineer, and why are they important?

To thrive as an Assistant Digital Verification Engineer, you need a solid understanding of digital design fundamentals, computer architecture, and a relevant degree in electrical or computer engineering. Familiarity with verification languages like SystemVerilog or UVM, along with experience using simulation and debugging tools such as ModelSim or VCS, is typically required. Strong analytical thinking, problem-solving ability, and effective communication skills help you collaborate with design teams and troubleshoot complex issues. These skills and qualities are crucial for ensuring reliable hardware designs and seamless project execution in a fast-paced engineering environment.

What are some common challenges faced by an assistant digital verification engineer during the verification process?

One common challenge for Assistant Digital Verification Engineers is ensuring comprehensive test coverage while meeting tight project deadlines. Balancing the need to identify edge cases and potential design bugs with limited simulation time can be demanding. Collaborating effectively with design and verification teams to clarify specifications and debug complex issues is also essential. Adapting quickly to evolving verification methodologies and tools is key to success in this role.

What is the difference between Assistant Digital Verification Engineer vs Digital Verification Engineer?

AspectAssistant Digital Verification EngineerDigital Verification Engineer
Required CredentialsBachelor's degree in Electrical Engineering or related field; some certificationsBachelor's or Master's degree; professional certifications often preferred
Work EnvironmentEntry-level, team support, supervised tasksMore independent, complex verification tasks
Employer & Industry UsageSemiconductor, electronics companies, R&D teamsSame industries, higher responsibility roles

The Assistant Digital Verification Engineer typically supports verification activities under supervision, focusing on learning and assisting with testing processes. In contrast, the Digital Verification Engineer handles more complex verification tasks independently, ensuring the functionality of digital designs. Both roles are essential in the verification process, but they differ in experience level and responsibility.

What are the most commonly searched types of Digital Verification Engineer jobs in California?

The most popular types of Digital Verification Engineer jobs in California are:

What cities in California are hiring for Assistant Digital Verification Engineer jobs?

Cities in California with the most Assistant Digital Verification Engineer job openings:

Assistant Digital Verification Engineer jobs near you
Infographic showing various Assistant Digital Verification Engineer job openings in California as of August 2026, with employment types broken down into 1% As Needed, 74% Full Time, 21% Part Time, 1% Temporary, and 3% Contract. Highlights an 98% Physical, 1% Hybrid, and 1% Remote job distribution.

Principal Engineer, Digital Verification and Emulation

Ayar Labs

San Jose, CA

$200K - $250K/hr

Full-time

Re-posted 2 days ago

Job description

Principal Engineer, Digital Verification amp; Emulation

Location: San Jose, CA — on-site
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics, or CPO, we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry leaders including NVIDIA, AMD, MediaTek and Intel, and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to enabling next-generation AI scale-up architectures.

We are seeking a Principal Engineer, Digital Verification amp; Emulation to lead verification and hardware-assisted validation for our next-generation silicon photonic chip. This role will focus on digital verification, emulation bring-up, mixed-signal-aware verification, real-number modeling, and software-driven pre-silicon validation. This is a senior individual-contributor technical leadership role working closely with architecture, RTL design, analog/mixed-signal, firmware, software, systems, and validation teams.
Essential Functions
  • Lead hardware-assisted verification using emulation platforms such as Synopsys ZeBu, Cadence Palladium, Siemens Veloce, or equivalent.
  • Own emulator bring-up, compile/debug flows, model mapping, debug visibility, runtime optimization, and emulation regression execution.
  • Build reusable verification environments for complex IP blocks, subsystems, and SoC-level designs using SystemVerilog, checkers, monitors, scoreboards, transactors, memory models, bus-functional models, and emulation-ready test infrastructure.
  • Adapt simulation environments for emulation and acceleration, including synthesizable components, test migration, and emulator-friendly verification methodology.
  • Develop, integrate, and validate real-number models, behavioral models, and mixed-signal abstraction models for analog/digital interface verification.
  • Partner with firmware and software teams to run pre-silicon workloads, diagnostics, register tests, traffic generation, and long-running system scenarios on emulation platforms.
  • Collaborate with architects and RTL designers to define verification plans, identify design risks, improve testability, and ensure readiness for simulation, emulation, and tape-out.
  • Debug complex failures across RTL, verification infrastructure, emulation models, firmware, embedded software, and mixed-signal behavioral models.
  • Define and track functional coverage, code coverage, assertions, verification metrics, exclusions, waivers, and signoff criteria.
  • Use assertions and formal techniques selectively for control logic, interfaces, reset behavior, CDC/RDC-sensitive logic, and difficult corner cases.
  • Develop scripts, flows, dashboards, and automation for regressions, emulation builds, job scheduling, log analysis, performance tracking, and coverage reporting.
  • Mentor engineers, conduct technical reviews, and drive verification methodology across the team.
Required Qualifications
  • BS in Electrical Engineering, Computer Engineering, or related field with 12+ years of relevant ASIC/SoC verification experience, or equivalent experience.
  • 6+ years of hands-on experience with hardware emulation or acceleration platforms such as Synopsys ZeBu, Cadence Palladium, Siemens Veloce, or equivalent. Experience should include bringing up complex digital designs in emulation, debugging emulation builds, migrating simulation tests to emulation, supporting long-running workloads, improving debug visibility, and working with emulation-ready components such as transactors, checkers, memory models, and bus-functional models.
  • 12+ years of digital verification experience across complex IP, subsystem, or SoC-level designs, from verification planning through debug, coverage, and signoff closure. Strong SystemVerilog skills are required; familiarity with UVM is expected, but this role is not limited to UVM testbench development. Experience with real-number models, behavioral models, mixed-signal abstraction models, assertions, or selective use of formal techniques is highly valuable.
  • Strong coding and automation skills using Python, Tcl, Perl, Shell, Make, or similar tools. Experience developing verification flows, regression automation, emulation build scripts, log analysis tools, coverage reporting, dashboards, or debug utilities is expected. Experience with C, C++, SystemC, Python, or MATLAB models for reference modeling or scoreboarding is a plus.
  • Strong hardware understanding, including SoC interfaces and protocols such as AMBA AXI/AHB/APB, PCIe, UCIe, Ethernet, SPI/I2C, memory-mapped buses, or similar high-speed interfaces. Experience with multiple clock domains, reset domains, clock dividers, asynchronous interfaces, CDC/RDC-sensitive logic, firmware interaction, and digital logic that controls or interfaces with analog/mixed-signal blocks is highly desirable.
Salary range: $190,000 - $250,000
NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.

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