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Assistant Computer Chip Engineer Jobs in Poway, CA

Sivaltech

Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Verify complex IPs and SoCs at block, subsystem, and chip level. * Work closely with RTL designers ... Education Bachelor''s or Master''s degree in Electronics Engineering, Computer Engineering, or a ...

InnoPhase IoT

Senior SoC STA Engineer

San Diego, CA · On-site

$144K - $148K/yr

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline (Master's degree preferred). * 10+ years of hands-on experience in chip-level STA ownership and full timing ...

Marvell

Principal Digital Design Engineer

San Diego, CA · On-site

$144K/yr

Work closely with system and chip architects to design industrial quality implementations ... Or Master's/PhD in Computer Science, Electrical Engineering or related fields with 5-10+ years of ...

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All JobsComputer Chip Engineer JobsAssistant Computer Chip Engineer JobsAssistant Computer Chip Engineer Jobs in Poway, CA

Assistant Computer Chip Engineer information

See Poway, CA salary details

$33.8K

$90.8K

$137.6K

How much do assistant computer chip engineer jobs pay per year?

As of Aug 11, 2026, the average yearly pay for assistant computer chip engineer in Poway, CA is $90,792.00, according to ZipRecruiter salary data. Most workers in this role earn between $72,100.00 and $106,900.00 per year, depending on experience, location, and employer.

What is the difference between Assistant Computer Chip Engineer vs Hardware Design Engineer?

AspectAssistant Computer Chip EngineerHardware Design Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields
Work EnvironmentResearch labs, semiconductor companies, tech firmsDesign firms, semiconductor companies, tech corporations
Employer & Industry UsageCommon in tech and semiconductor industriesUsed in hardware development and chip design sectors
Common Search & ComparisonYesYes

The Assistant Computer Chip Engineer typically supports chip development through testing and analysis, often working under senior engineers. Hardware Design Engineers focus on designing and developing the physical architecture of chips. Both roles require similar educational backgrounds and are integral to the semiconductor industry, but they differ mainly in responsibilities and focus areas.

What job categories do people searching Assistant Computer Chip Engineer jobs in Poway, CA look for? The top searched job categories for Assistant Computer Chip Engineer jobs in Poway, CA are:
What cities near Poway, CA are hiring for Assistant Computer Chip Engineer jobs? Cities near Poway, CA with the most Assistant Computer Chip Engineer job openings:
Assistant Computer Chip Engineer jobs near you
Infographic showing various Assistant Computer Chip Engineer job openings in Poway, CA as of August 2026, with employment types broken down into 1% As Needed, 82% Full Time, 13% Part Time, 3% Contract, and 1% Nights. Highlights an 80% Physical, 1% Hybrid, and 19% Remote job distribution, with an average salary of $90,792 per year, or $43.6 per hour.

Design Verification Engineer

Sivaltech

San Diego, CA • On-site

$144K - $176K/yr

Other

Posted 7 days ago

Job description

Design Verification Engineer

Location: Bay Area, CA (Onsite/Hybrid)
Experience: 8+ Years

Job Summary

We are seeking an experienced Design Verification Engineer with strong expertise in ASIC/SoC verification to join our semiconductor team. The ideal candidate will have extensive experience in SystemVerilog, UVM, and protocol verification, with a proven track record of developing robust verification environments and achieving coverage closure.

Key Responsibilities

  • Develop and execute comprehensive verification plans for ASIC/SoC designs.

  • Build reusable UVM-based verification environments, testbenches, scoreboards, checkers, and assertions.

  • Create and execute directed and constrained-random test cases.

  • Perform functional, code, assertion, and toggle coverage analysis and drive coverage closure.

  • Debug RTL and simulation issues in collaboration with design teams.

  • Verify complex IPs and SoCs at block, subsystem, and chip level.

  • Work closely with RTL designers, architects, and physical design teams throughout the development lifecycle.

  • Participate in regression execution, bug tracking, and verification sign-off.

Required Skills

  • 8+ years of ASIC/SoC Design Verification experience.

  • Strong expertise in SystemVerilog and UVM.

  • Excellent knowledge of Verilog and digital design fundamentals.

  • Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens QuestaSim.

  • Strong debugging and scripting skills using Python, Perl, Shell, or Tcl.

  • Experience with assertions (SVA), constrained-random verification, and functional coverage.

  • Familiarity with version control systems such as Git.

Preferred Experience

  • Chip-level and SoC verification.

  • Verification of high-speed bus protocols such as AXI, AHB, APB, PCIe, USB, Ethernet, DDR, MIPI, or UCIe.

  • Low-power verification using UPF/CPF.

  • Experience with emulation or FPGA prototyping is a plus.

Education

Bachelor''s or Master''s degree in Electronics Engineering, Computer Engineering, or a related field.

Employment Type: Full-Time

If you are passionate about ASIC verification and have hands-on experience with modern verification methodologies, we''d love to hear from you.

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