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Asic Verification Engineer Remote Jobs in Idaho (NOW HIRING)

Stantec

Fire Protection Engineer (Remote or Hybrid)

Boise, ID · On-site +1

$79K - $106K/yr

We value flexibility-remote or hybrid work options may be available depending on the candidate and ... Verify compliance with applicable codes and engineering standards and practices. * Work with other ...

Booz Allen Hamilton, Inc.

$61K - $141K/yr

Remote Work: Hybrid Job Number: R0245980 Location: Arnold AFB,TN,US Share job via: Share Systems ... Experience with requirements validation and verification * Experience with a gated design review ...

Sargent & Lundy

Electrical Engineer Manager

Boise, ID · On-site +1

$145K - $222K/yr

... field verification of designs. This position is expected to start remote with the expectation to ... A BSEE degree from an ABET-accredited engineering program is required and an emphasis in power ...

Sargent & Lundy

Electrical Engineer Manager

Boise, ID · On-site +1

$145K - $222K/yr

... field verification of designs. This position is expected to start remote with the expectation to ... A BSEE degree from an ABET-accredited engineering program is required and an emphasis in power ...

Sargent & Lundy

Lead Electrical Engineer

Boise, ID · On-site +1

$152K - $158K/yr

... field verification of designs. This position is expected to start remote with the expectation to ... A BSEE degree from an ABET-accredited engineering program is required and an emphasis in power ...

Sargent & Lundy

Lead Electrical Engineer

Boise, ID · On-site +1

$152K - $158K/yr

... field verification of designs. This position is expected to start remote with the expectation to ... A BSEE degree from an ABET-accredited engineering program is required and an emphasis in power ...

GFT.

OE Transmission Line Engineers

Boise, ID · On-site +1

$100K - $140K/yr

GFT is seeking an OE Transmission Line Engineer to join our Power Business Group! If you are in ... However for the right candiate, this would be a remote position. Joining the power team at GFT ...

Circle

Manager, Software Engineering

Boise, ID · On-site +1

$195K - $257K/yr

You have experience managing remote teams * The ability to thrive on a fast pace environment with ... Additionally, Circle participates in the E-Verify Program in certain locations, as required by law.

Booz Allen Hamilton, Inc.

$55K - $126K/yr

Remote Work: Hybrid Job Number: R0246765 Location: Arnold AFB,TN,US Share job via: Share ... Assisting with maintaining configuration baselines, processing engineering changes, supporting CCB ...

Booz Allen Hamilton, Inc.

$61K - $141K/yr

Remote Work: Hybrid Job Number: R0246774 Location: Arnold AFB,TN,US Share job via: Share OT and ICS ... That's why we need you, an OT security engineer who knows how to craft and implement comprehensive ...

Sony

$50/hr

You will receive support from internal scientists and engineers in your efforts. Required ... Working Location Location flexible (Tokyo, NYC, remote) The target hourly rate for this internship ...

Sony

$50/hr

You will receive support from internal scientists and engineers in your efforts. Required ... Working Location Location flexible (Tokyo, NYC, remote) The target hourly rate for this internship ...

Sony

$50/hr

You will receive support from internal scientists and engineers in your efforts. Required ... Working Location Location flexible (Tokyo, NYC, remote) The target hourly rate for this internship ...

Sony

$50/hr

You will receive support from internal scientists and engineers in your efforts. Required ... Working Location Location flexible (Tokyo, NYC, remote) The target hourly rate for this internship ...

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Asic Verification Engineer Remote information

What does an ASIC Verification Engineer do?

An ASIC Verification Engineer is responsible for ensuring that an Application-Specific Integrated Circuit (ASIC) design functions as intended before it is manufactured. They develop and implement test plans, create verification environments using hardware description and verification languages like SystemVerilog or UVM, and run simulations to detect design flaws. Working remotely, these engineers collaborate with design teams using digital tools and communication platforms to review specifications, debug issues, and validate functionality. Their work is critical to reducing errors, saving costs, and ensuring high-quality chip production.

What are the key skills and qualifications needed to thrive as an ASIC Verification Engineer remote?

To thrive as an ASIC Verification Engineer (Remote), you need a solid background in digital design, verification methodologies, and hardware description languages such as Verilog or VHDL, often supported by a degree in electrical or computer engineering. Proficiency with simulation tools (e.g., Synopsys VCS, Cadence Xcelium), scripting languages (Python, Perl), and familiarity with UVM or SystemVerilog is typically required. Strong problem-solving skills, effective communication, and the ability to work independently and collaboratively in distributed teams are valuable soft skills. These competencies are crucial for ensuring robust chip validation, efficient remote collaboration, and successful project delivery in complex hardware development environments.

What are the main challenges of working remotely as an ASIC Verification Engineer, and how can they be addressed?

One of the main challenges of working remotely as an ASIC Verification Engineer is effective collaboration with design and verification teams, especially when debugging complex issues that benefit from real-time, face-to-face communication. Additionally, accessing hardware labs or simulation environments may require coordination with on-site colleagues. To address these challenges, it’s important to leverage video conferencing, screen sharing, and collaborative project management tools. Proactively communicating your progress and questions, and establishing regular check-ins with your team, can help ensure alignment and maintain productivity in a remote setup.

What is the difference between Asic Verification Engineer Remote vs Asic Design Engineer?

AspectAsic Verification Engineer RemoteAsic Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA/ASIC verification certificationsBachelor's/Master's in Electrical Engineering or Computer Engineering; VLSI design certifications
Work EnvironmentRemote, collaborative teams, virtual toolsTypically in-office or hybrid, design labs, CAD tools
Industry UsageCommon in semiconductor, electronics, and tech companies

While both roles require a strong background in VLSI and digital design, Asic Verification Engineers focus on testing and validating ASIC designs remotely, whereas Asic Design Engineers are involved in creating and designing ASICs, often working on-site. The roles share similar credentials but differ in daily tasks and work environment.

What are popular job titles related to Asic Verification Engineer Remote jobs in Idaho?

For Asic Verification Engineer Remote jobs in Idaho, the most frequently searched job titles are:

What job categories do people searching Asic Verification Engineer Remote jobs in Idaho look for?

The top searched job categories for Asic Verification Engineer Remote jobs in Idaho are:

What cities in Idaho are hiring for Asic Verification Engineer Remote jobs?

Cities in Idaho with the most Asic Verification Engineer Remote job openings:

Asic Verification Engineer Remote jobs near you
Infographic showing various Asic Verification Engineer Remote job openings in Idaho as of August 2026, with employment types broken down into 91% Full Time, 6% Part Time, and 3% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution.

Senior Principal ASIC FPGA Engineer

General Dynamics Mission Systems, Inc

Boise, ID • On-site, Remote

$191K - $212K/yr

Full-time

Re-posted 19 days ago

General Dynamics Mission Systems rating

8.1

Company rating: 8.1 out of 10

Based on 31 frontline employees who took The Breakroom Quiz

113th of 247 rated software companies

Job description

Basic Qualifications
Education Requirements:
Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 10 years of relevant experience; or Master's degree plus a minimum of 8 years of relevant experience.
Clearance Requirements:
Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.
Responsibilities for this Position
We're looking for a seasoned ASIC Lead Engineer who has been there - not just written RTL, but fought through timing closure under pressure, untangled bus fabric correctness issues, debugged reset sequencing nightmares, and brought complex silicon to tape-out. This is a hands-on technical leadership role for someone who has lived the full ASIC design lifecycle and has the scars to prove it.
If your career has been primarily running P&R tools, this probably isn't the right fit. We need an RTL designer at heart - someone who thinks in architecture and microarchitecture first, and understands the downstream implications of every design decision.
The right candidate is a self-starter who operates with minimal supervision - someone who takes ownership of their domain, drives progress independently, and brings solutions rather than waiting to be directed. You'll be well-integrated within a collaborative team, but we expect you to lead from the front, not follow from behind.
What You'll Do
  • Own the architecture - Define the ASIC/FPGA technical approach from concept through silicon, including system
    partitioning, microarchitecture, and interface definition
  • Drive RTL design - Lead detailed RTL development with a focus on correctness: bus fabric integrity, clock domain
    crossings, reset order-of-operations, and design-for-verification
  • Close timing - Navigate synthesis, place and route, and static timing analysis with deep understanding of what it
    takes to meet timing in advanced process nodes - not just run the tools, but fix the problems
  • Lead verification - Serve as the primary point of contact for verification activities; develop and own test and
    simulation plans that establish rigorous functional criteria; verify results and drive closure on failures
  • Triage and track - Own JIRA triage for the team: reviewing incoming issues, prioritizing work items, and ensuring
    the backlog reflects program reality
  • Lead code reviews - Conduct and lead RTL code reviews, setting the technical bar and providing actionable, constructive feedback to engineers at all levels
  • Support program planning - Contribute to Integrated Master Schedule (IMS) development and Earned Value (EV)
    reporting; provide accurate technical input on task status, completion criteria, and schedule risk
  • Evaluate process flows - High-level design through GDSII, including synthesis, P&R, timing, power analysis, and DFT considerations
  • Guide technology selection - Assess foundry technologies, device libraries, IP cores, and EDA tooling to inform
    design decisions
  • Support proposals and subcontracts - Lead ASIC/FPGA technical approach on large proposals; may serve as book boss on medium proposals; manage technical subcontracts including SOW development, source selection, and work product
    acceptance
  • Grow the team - Mentor junior and mid-level engineers; contribute to the development and improvement of
    organizational ASIC/FPGA design processes
  • Collaborate broadly - Participate in multi-divisional or multi-company Integrated Product Teams and working groups

What We're Looking For
Experience
  • 10-15+ years of ASIC/FPGA design experience, with the majority spent as an RTL designer - not in a purely backend or physical design role
  • Proven experience taking designs through full ASIC tape-out, including timing closure, physical verification, and
    post-silicon bring-up
  • Deep familiarity with FinFET process nodes (7nm, 5nm, or similar) - understanding the nuances of FinFET vs. planar
    technology is a meaningful differentiator for this role
  • Experience with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent)
  • Demonstrated expertise in:
    • RTL design and microarchitecture definition
    • Bus fabric design and correctness verification
    • Clock domain crossing (CDC) analysis and closure
    • Reset sequencing and order-of-operations validation
    • Timing closure at advanced nodes - not just constraint writing, but root cause analysis and fixing
    • Power analysis and optimization

Skills & Knowledge
  • Expert-level understanding of ASIC/FPGA engineering concepts, RTL coding practices, and synthesis flows
  • Strong familiarity with industry-standard EDA tools (synthesis, simulation, formal verification, STA)
  • Demonstrated ability to operate independently - identifying problems, driving resolution, and keeping work moving
    without requiring day-to-day direction
  • Ability to evaluate vendor and foundry capabilities to support product development decisions
  • Track record of innovative technical contributions - not just executing to spec, but shaping the approach
  • Solid understanding of organizational processes and the ability to apply them pragmatically across a program
    lifecycle, including schedule management and earned value inputs
  • Proficiency in JIRA for issue tracking and backlog management
  • Proficiency in Microsoft Office for documentation and communication

Why This Role
You won't be handed a spec and told to code. You'll help shape what we build, how we build it, and what it takes to get it right. This is a role with real technical latitude, the kind of program impact that shows up in new business, and a team that values engineers who know the difference between running the tools and knowing what the tools are telling you. If you're the kind of engineer who sees a gap and fills it - without being asked - this is the role for you.
#LI-JH1
#LI-Hybrid
Salary Note
This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.
Combined Salary Range
USD $191,146.00 - USD $212,053.00 /Yr.
Company Overview
General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!
Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

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