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Asic Physical Design Automation Engineer Jobs (NOW HIRING)

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... Develop and maintain scripts and automation to improve flow efficiency and consistency. * Support ...

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... Develop and maintain scripts and automation to improve flow efficiency and consistency. * Support ...

ASIC Physical Design Lead

Dayton, OH · On-site

$132K - $136K/yr

Mentor, coach, and guide engineers in methodology, debug, and best practices. * Champion continuous ... ASIC Physical Design, with a strong track record of multiple tape‑outs at advanced technology ...

ASIC Physical Design Engineer

New York, NY · On-site

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to ...

ASIC Physical Design Engineer

New York, NY · On-site

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to ...

ASIC Physical Design Lead

Fayetteville, AR · On-site

$130K - $134K/yr

Mentor, coach, and guide engineers in methodology, debug, and best practices. * Champion continuous ... ASIC Physical Design, with a strong track record of multiple tape‑outs at advanced technology ...

ASIC Physical Design Lead

Columbus, OH · On-site

$127K - $130K/yr

Mentor, coach, and guide engineers in methodology, debug, and best practices. * Champion continuous ... ASIC Physical Design, with a strong track record of multiple tape‑outs at advanced technology ...

$149K - $213K/yr

Execute and support the backend ASIC physical design flow, including synthesis, floorplanning ... Use scripting and automation to improve design, verification, implementation, analysis, and ...

New

ASIC Digital Physical Design Engineer Join a dynamic team where you will execute ASIC digital ... Strong scripting and automation skills using Tcl, Python, Perl, or shell scripting. Additional ...

New

ASIC Digital Physical Design Engineer Join a dynamic team where you will execute ASIC digital ... Strong scripting and automation skills using Tcl, Python, Perl, or shell scripting. Additional ...

New

Nokia of America Corporation , Sr ASIC Physical Design Engineer (Multiple Positions), Sunnyvale, CA ... and automation; * Must have 5 years of experience using static timing analysis (STA) and power ...

Showing results 41-60

Asic Physical Design Automation Engineer information

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$65K

$97.1K

$155K

How much do asic physical design automation engineer jobs pay per year?

As of Sep 13, 2026, the average yearly pay for asic physical design automation engineer in the United States is $97,090.00, according to ZipRecruiter salary data. Most workers in this role earn between $83,500.00 and $104,500.00 per year, depending on experience, location, and employer.

What are popular job titles related to Asic Physical Design Automation Engineer jobs?

For Asic Physical Design Automation Engineer jobs, the most frequently searched job titles are:

Infographic showing various Asic Physical Design Automation Engineer job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 76% Full Time, 18% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 98% Physical, 1% Hybrid, and 1% Remote job distribution, with an average salary of $97,090 per year, or $46.7 per hour.

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

Austin, TX • On-site

SpaceX
Aerospace Product and Parts Manufacturing • 1 - 5K employees

Full-time

Re-posted 19 days ago


SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 152 frontline employees who took The Breakroom Quiz


Job description

SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)

At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

  • Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • Develop/improve physical design methodologies and automation scripts for various implementation steps
  • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
  • Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 5+ years of ASIC and/or physical design flow development experience in industry

PREFERRED SKILLS AND EXPERIENCE:

  • Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
  • Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
  • Knowledge of deep sub-micron FinFET and CMOS solid state physics
  • Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
  • Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
  • Familiar with CMOS analog circuit and physical design
  • Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
  • Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
  • Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:    

  • Ability to work extended hours and weekends as needed to meet critical project milestones   

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About SpaceX

Sourced by ZipRecruiter

Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US