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Asic Engineering Jobs in Cary, IL (NOW HIRING)

Eliyan

PD - Principal, Physical Design

Mundelein, IL

As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... Qualifications: * 8 to 12 years ASIC physical design experience owning floorplanning integration ...

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All JobsAsic Engineering JobsAsic Engineering Jobs in Cary, IL

Asic Engineering information

See Cary, IL salary details

$83.7K

$160.5K

$169.9K

How much do asic engineering jobs pay per year?

As of Aug 18, 2026, the average yearly pay for asic engineering in Cary, IL is $160,522.00, according to ZipRecruiter salary data. Most workers in this role earn between $168,400.00 and $168,400.00 per year, depending on experience, location, and employer.

What is the difference between Asic Engineering vs FPGA Design?

AspectAsic EngineeringFPGA Design
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fields; often certifications in ASIC designBachelor's or Master's in Electrical Engineering, Digital Design, or related fields; certifications less common
Work EnvironmentDesigning custom chips in semiconductor labs or design houses; involves hardware and software integrationDeveloping programmable logic designs in labs or FPGA development environments; focuses on reconfigurable hardware
Industry UsageUsed in high-volume consumer electronics, telecom, and automotive industries for custom chip solutionsCommon in prototyping, testing, and specialized applications across various industries

Asic Engineering and FPGA Design share foundational knowledge in digital logic and hardware description languages. However, Asic Engineers focus on designing permanent, high-volume chips, while FPGA Designers work with reconfigurable hardware for testing and specialized tasks. Both roles require similar educational backgrounds but differ in application and design processes.

What are popular job titles related to Asic Engineering jobs in Cary, IL?

For Asic Engineering jobs in Cary, IL, the most frequently searched job titles are:

What cities near Cary, IL are hiring for Asic Engineering jobs?

Cities near Cary, IL with the most Asic Engineering job openings:

Asic Engineering jobs near you
Infographic showing various Asic Engineering job openings in Cary, IL as of August 2026, with employment types broken down into 84% Full Time, 13% Part Time, 2% Contract, and 1% Nights. Highlights an 85% Physical, 5% Hybrid, and 10% Remote job distribution, with an average salary of $160,522 per year, or $77.2 per hour.

PD - IP Lead - Sr Staff, Physical Design

Eliyan

Mundelein, IL

$138K - $142K/yr

Full-time

Re-posted 10 days ago

Job description

Join the leading chiplet startup! As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will drive the development of cutting-edge ASICs from RTL to GDSII.  You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products. In this role, you will oversee and optimize the entire design flow, including synthesis, place-and-route (PNR), static timing analysis (STA), electromigration/IR drop analysis (EM/IR), and physical verification (PV – DRC, LVS, Antenna). You will also focus on developing and improving design flows and methodologies to ensure high-quality, on-time delivery. We offer a fun work environment with excellent benefits.
Responsibilities:
  • Define and execute IP block and partition physical design strategy across projects, aligning schedules, resources, and milestones to company tapeout goals.
  • Lead mixed signal placement and routing, enforcing analog keepouts, shielding, and DRC aware methodologies while integrating digital logic cleanly.
  • Own system and block integration for floorplanning, power, placement, CTS, and constraints, ensuring consistent interfaces across hierarchy and reuse
  • Drive end to end IP physical implementation from RTL handoff through GDSII, managing iterations, ECOs, and closure plans across corners
  • Develop and maintain block specific flow customizations for synthesis, PNR, EM IR, STA, and physical verification to improve QoR and predictability
  • Deliver robust constraints methodology, pushing timing intent from system to block and back, maintaining mode and corner correctness for signoff
  • Run and close subsystem signoff including STA, EM IR, SI, DRC, LVS, antenna, and metal fill, meeting reliability and manufacturability requirements
  • Optimize clock architecture and CTS for skew, latency, and power, including skew group definitions and balancing across library corners
  • Collaborate with front end, DFT, packaging, and manufacturing to resolve integration risks, test mode impacts, and physical interface requirements
  • Provide clear status, risk, and mitigation reporting to leadership, using metrics driven dashboards for PPA, convergence, and schedule predictability
Minimum Qualifications:
  • Expertise in physical design, timing closure, and signoff for small to large ASIC IP blocks, including mixed signal integration and subsystem closure ownership
  • Strong hands-on experience with floorplanning, power planning, placement, CTS, routing, EM IR, STA, and PV signoff across MMMC scenarios
  • Proven ability to improve flows through automation and scripting, with disciplined debug skills and data driven QoR and runtime optimization mindset
  • Excellent cross functional leadership and communication skills to drive alignment, technical reviews, and closure decisions under aggressive timelines

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.