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Asic Design Manager Jobs in Edmonds, WA (NOW HIRING)

SpaceX

RFIC Layout Designer (RFIC Engineering)

Redmond, WA · On-site

$120K - $175K/yr

... ASIC design, firmware, pre-silicon verification, post-silicon validation, product engineering ... Experience managing revision control systems * Experience with circuit design * Understanding of ...

Amazon

FPGA Engineer, Amazon LEO OISL

Redmond, WA · On-site

$145K - $187K/yr

... with ASIC/FPGA design and verification tools - 3+ years of experience in ASIC/FPGA design ... management, build processes, testing, and operations experience - Experience developing python ...

Amazon

FPGA Engineer, Amazon LEO OISL

Redmond, WA · On-site

$145K - $187K/yr

... with ASIC/FPGA design and verification tools - 3+ years of experience in ASIC/FPGA design ... management, build processes, testing, and operations experience - Experience developing python ...

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All JobsAsic Design JobsAsic Design Manager JobsAsic Design Manager Jobs in Edmonds, WA

Asic Design Manager information

See Edmonds, WA salary details

$46.1K

$125.7K

$221.3K

How much do asic design manager jobs pay per year?

As of Aug 23, 2026, the average yearly pay for asic design manager in Edmonds, WA is $125,726.00, according to ZipRecruiter salary data. Most workers in this role earn between $91,700.00 and $158,100.00 per year, depending on experience, location, and employer.

What does an ASIC Design Manager do?

An ASIC Design Manager oversees the design and development of Application Specific Integrated Circuits (ASICs), managing a team of engineers through the entire chip design process. They coordinate project timelines, ensure technical specifications are met, and facilitate communication between design, verification, and manufacturing teams. Their role also involves resource planning, risk management, and ensuring that the final product meets performance, cost, and quality targets.

What are the key skills and qualifications needed to thrive as an ASIC Design Manager?

To thrive as an ASIC Design Manager, you need expertise in digital and analog ASIC design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), verification methodologies, and knowledge of relevant design flows is crucial. Strong leadership, communication, and problem-solving skills help manage teams and coordinate with cross-functional stakeholders. These competencies ensure high-quality chip designs are delivered on time and meet performance and cost targets, which is vital for organizational success.

What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?

ASIC Design Managers often navigate the complexities of coordinating multidisciplinary teams, including digital, analog, verification, and physical design engineers. One common challenge is ensuring clear communication across these specialties to maintain alignment on project goals, timelines, and technical requirements. Additionally, managing shifting priorities, resolving technical bottlenecks, and balancing resource allocation are frequent hurdles. Successful managers foster collaboration, set clear expectations, and leverage structured project management practices to keep teams productive and motivated.

What is the difference between Asic Design Manager vs Asic Design Engineer?

AspectAsic Design ManagerAsic Design Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, and coordinates with stakeholdersPerforms ASIC design, coding, simulation, and verification tasks
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification skills
ExperienceTypically 8+ years in ASIC design, with leadership experienceUsually 2-5 years in ASIC design roles
Work EnvironmentDesign teams, project planning, cross-functional collaborationDesign labs, simulation environments, coding and testing

The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.

What job categories do people searching Asic Design Manager jobs in Edmonds, WA look for?

The top searched job categories for Asic Design Manager jobs in Edmonds, WA are:

Asic Design Manager jobs near you
Infographic showing various Asic Design Manager job openings in Edmonds, WA as of August 2026, with employment types broken down into 82% Full Time, 16% Part Time, and 2% Contract. Highlights an 84% Physical, 3% Hybrid, and 13% Remote job distribution, with an average salary of $125,726 per year, or $60.4 per hour.

Sr. RFIC Layout Designer (RFIC Engineering)

United States Digital Space LLC

Redmond, WA • On-site

$135 - $195/hr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 5 days ago

Job description

the company was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today the company is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

SR. RFIC LAYOUT DESIGNER (RFIC ENGINEERING)

At the company we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best‑in‑class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking motivated, proactive, and intellectually curious engineers who will work alongside world‑class cross‑disciplinary teams (systems architecture, ASIC design, firmware, pre‑silicon verification, post‑silicon validation, product engineering, manufacturing/production, and more). In this role, you will be on a team working on multiple silicon projects that are driving more integration, lower power, mixed signal architectures and advanced silicon technology for deployment in space and ground infrastructures. You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and RFIC designs.

RESPONSIBILITIES:
  • Work with the integrated circuit designers and chip leads to determine the chip floor plan; this includes strategies for power and ground distribution as well as working with packaging engineer to determine pad locations
  • Accurately estimate the schedule for the layout work and identify areas of complexity that need early investigation
  • Perform layout of custom RF and analog circuit blocks with attention to matching and minimizing parasitic capacitance in the layout
  • Perform design rule checking, electrical rule checking and layout versus schematic checks and resolve errors
  • Perform top‑level layout integration with electrostatic discharge structures and pad assembly and perform final tape out (including density fill, running design for manufacturability checks and sharing GDS with the foundry)
  • Work with EDA suppliers to trial new tools and features
  • Generate guides and demos for others in the team to showcase improvements in layout technique
BASIC QUALIFICATIONS:
  • Bachelor’s degree in electrical or computer engineering and 5+ years of professional experience as an IC layout designer; OR 8+ years of professional experience with integrated circuit layout design in lieu of a degree
PREFERRED SKILLS AND EXPERIENCE:
  • Strong analog layout skills
  • Experience in advanced node IC layouts such as 22nm, 16nm, 7nm, 5nm or below
  • Experience in layout of circuits with frequencies up to 50GHz
  • Experience in layout of sensitive RF blocks such as low noise amplifiers, voltage controlled oscillators and mixers
  • Experience with skill programming
  • Experience with shell scripting, Perl, Python or similar language
  • Experience managing revision control systems
  • Experience with circuit design
  • Understanding of layout considerations for device matching, coupling and noise isolation
  • Working knowledge of Linux
  • Excellent communication skills (both oral and written) are required
  • Able to work independently on challenging problems
ADDITIONAL REQUIREMENTS:
  • Ability to work extended hours and weekends as needed to meet critical milestones
COMPENSATION AND BENEFITS:

Pay range:

Layout Designer/Senior: $135,000.00 - $195,000.00 per year

Your actual level and base salary will be determined on a case‑by‑case basis and may vary based on the following considerations: job‑related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at the company. You may also be eligible for long‑term incentives, in the form of company stock, stock options, or long‑term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long‑term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

ITAR REQUIREMENTS:
  • To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR.

the company is an Equal Opportunity Employer; employment with the company is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of the company’s Affidative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to hr@unitedstatesdigital.space.

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