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Asic Design Manager Jobs in Washington (NOW HIRING)

Digital Design SME

Mclean, VA ยท On-site

$176K - $282K/yr

Application Specific Integrated Circuit (ASIC) design & fabrication, microprocessor design ... Lead and manage project teams and initiatives. **This role requires the candidate to perform duties ...

Digital Design SME

Mclean, VA ยท On-site

$176K - $282K/yr

Application Specific Integrated Circuit (ASIC) design & fabrication, microprocessor design ... Lead and manage project teams and initiatives. **This role requires the candidate to perform duties ...

Application Specific Integrated Circuit (ASIC) design & fabrication, microprocessor design ... Lead and manage project teams and initiatives. **This role requires the candidate to perform duties ...

Lead Firmware Engineer

Arlington, VA ยท On-site

$157K - $224K/yr

Coordinating with program managers and technical leads to manage task schedules and budgets ... Proficient with FPGA or ASIC RTL design entry * Strong background and experience with industry best ...

Lead Firmware Engineer

Arlington, VA ยท On-site

$157K - $224K/yr

Coordinating with program managers and technical leads to manage task schedules and budgets ... Proficient with FPGA or ASIC RTL design entry * Strong background and experience with industry best ...

Lead Firmware Engineer

Arlington, VA ยท On-site

$157K - $224K/yr

Coordinating with program managers and technical leads to manage task schedules and budgets ... Proficient with FPGA or ASIC RTL design entry * Strong background and experience with industry best ...

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Showing results 1-20

Asic Design Manager information

See Washington salary details

$47.6K

$129.7K

$228.2K

How much do asic design manager jobs pay per year?

As of Jul 28, 2026, the average yearly pay for asic design manager in Washington is $129,672.00, according to ZipRecruiter salary data. Most workers in this role earn between $94,600.00 and $163,100.00 per year, depending on experience, location, and employer.

What is the difference between Asic Design Manager vs Asic Design Engineer?

AspectAsic Design ManagerAsic Design Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, and coordinates with stakeholdersPerforms ASIC design, coding, simulation, and verification tasks
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification skills
ExperienceTypically 8+ years in ASIC design, with leadership experienceUsually 2-5 years in ASIC design roles
Work EnvironmentDesign teams, project planning, cross-functional collaborationDesign labs, simulation environments, coding and testing

The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.

What are the key skills and qualifications needed to thrive as an ASIC Design Manager, and why are they important?

To thrive as an ASIC Design Manager, you need expertise in digital and analog ASIC design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), verification methodologies, and knowledge of relevant design flows is crucial. Strong leadership, communication, and problem-solving skills help manage teams and coordinate with cross-functional stakeholders. These competencies ensure high-quality chip designs are delivered on time and meet performance and cost targets, which is vital for organizational success.

What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?

ASIC Design Managers often navigate the complexities of coordinating multidisciplinary teams, including digital, analog, verification, and physical design engineers. One common challenge is ensuring clear communication across these specialties to maintain alignment on project goals, timelines, and technical requirements. Additionally, managing shifting priorities, resolving technical bottlenecks, and balancing resource allocation are frequent hurdles. Successful managers foster collaboration, set clear expectations, and leverage structured project management practices to keep teams productive and motivated.

What does an ASIC Design Manager do?

An ASIC Design Manager oversees the design and development of Application Specific Integrated Circuits (ASICs), managing a team of engineers through the entire chip design process. They coordinate project timelines, ensure technical specifications are met, and facilitate communication between design, verification, and manufacturing teams. Their role also involves resource planning, risk management, and ensuring that the final product meets performance, cost, and quality targets.
What are the most commonly searched types of Asic Design jobs in Washington? The most popular types of Asic Design jobs in Washington are:
What are popular job titles related to Asic Design Manager jobs in Washington? For Asic Design Manager jobs in Washington, the most frequently searched job titles are:
What job categories do people searching Asic Design Manager jobs in Washington look for? The top searched job categories for Asic Design Manager jobs in Washington are:
Infographic showing various Asic Design Manager job openings in Washington as of July 2026, with employment types broken down into 20% As Needed, 68% Full Time, 9% Part Time, 2% Contract, and 1% Summer. Highlights an 85% Physical, 9% Hybrid, and 6% Remote job distribution, with an average salary of $129,672 per year, or $62.3 per hour.
FPGA/ASIC Design Engineer with Security Clearance

FPGA/ASIC Design Engineer with Security Clearance

Indotronix International Corp

Herndon, VA โ€ข On-site

$115/hr

Contractor

Posted 13 days ago


Job description

Job Title: FPGA/ASIC Design Engineer
Location: Herndon, VA
Duration: 12 Months
Pay: $115/hr on W2
Active Secret Clearance Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key design team, responsible for the delivery of FPGAs for defense applications. S/he will architect, implement FPGA design, with hands on design/debug with primarily Ethernet, I2C, SPI, AXI protocols. L3Harris has state-of-the-art EDA flows/methodologies including Mentor EDA: Simulator Questa Prime, Verification IP (QVIPs), UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, Synopsys (DC/Primetime/Synplify), Xilinx/Intel/Microchip EDA (Vivado/Libero/Quartus). We are a learning organization and have the capability to target all FPGA vendors and have ASIC front end capability, with mature design processes. This is a high impact role in the organization to ensure robust quality and delivery of communication products for National Security. Essential Functions: Derive FPGA design specifications from system requirements
Develop detailed FPGA architecture for implementation
Implement design in RTL (VHDL) and perform module level simulations
Perform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA)
Perform RTL quality using: Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC) , Static Formal EDA
Generate verification test plans and perform End to End Simulations
Support Board, FPGA bring up
Validate design through HW/SW integration test with test equipment
Support product collateral for NSA certification Qualifications: Bachelor of Science (BS) -Four year degree or Masters (MS) or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science)
3-5+ yearsโ€™ experience designing FPGA products with VHDL
Experience with Xilinx FPGAs and Vivado
Experience with Revision control system
Experience with Earned Value Management (EVM)
Good written, verbal, and presentation skills
Active DoD Security Clearance Preferred Additional Skills: Experience with mapping algorithms to architecture
Experience in C++ (OOP)
Experience with any of protocols : Ethernet, TCP/IP, PCIe, NVMe, USB
Experience with Xilinx SoC design with SDKs and PetaLinux OS
Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapult

Indotronix logo

About Indotronix

Sourced by ZipRecruiter

In 1986, Indotronix established itself in the staffing space. 22 years later, Avani entered the scene, offering consulting and technology development. Finally, in 2016, the two joined forces to begin delivering talent across all areas, from Staffing to Consulting to unique platform development.

Industry

Recruiting and staffing services

Company size

1,001 - 5,000 Employees

Headquarters location

Rochester, NY, US