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Asic Design Manager Jobs in Washington (NOW HIRING)

3B Staffing LLC

FPGA/ASIC Design Engineer

Reston, VA · On-site

$128K - $176K/yr

Technicall/Professional Reporting to the Manager, Engineering (ASIC/FPGA), the Design Engineer will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed ...

Peraton

Digital Design SME

Mclean, VA · On-site

$176K - $282K/yr

Application Specific Integrated Circuit (ASIC) design & fabrication, microprocessor design ... Lead and manage project teams and initiatives. **This role requires the candidate to perform duties ...

New

Peraton

Digital Design SME

Mclean, VA

$176K - $282K/yr

Application Specific Integrated Circuit (ASIC) design & fabrication, microprocessor design ... Lead and manage project teams and initiatives. **This role requires the candidate to perform duties ...

Peraton

Digital Design SME

Mclean, VA · On-site

$176K - $282K/yr

Application Specific Integrated Circuit (ASIC) design & fabrication, microprocessor design ... Lead and manage project teams and initiatives. **This role requires the candidate to perform duties ...

STR

Lead Firmware Engineer

Arlington, VA · On-site

$157K - $224K/yr

Coordinating with program managers and technical leads to manage task schedules and budgets ... Proficient with FPGA or ASIC RTL design entry * Strong background and experience with industry best ...

STR

Lead Firmware Engineer

Arlington, VA

$157K - $224K/yr

Coordinating with program managers and technical leads to manage task schedules and budgets ... Proficient with FPGA or ASIC RTL design entry * Strong background and experience with industry best ...

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All JobsAsic Design JobsAsic Design Manager JobsAsic Design Manager Jobs in Washington

Asic Design Manager information

See Washington salary details

$47.6K

$129.7K

$228.2K

How much do asic design manager jobs pay per year?

As of Jul 26, 2026, the average yearly pay for asic design manager in Washington is $129,672.00, according to ZipRecruiter salary data. Most workers in this role earn between $94,600.00 and $163,100.00 per year, depending on experience, location, and employer.

What is the difference between Asic Design Manager vs Asic Design Engineer?

AspectAsic Design ManagerAsic Design Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, and coordinates with stakeholdersPerforms ASIC design, coding, simulation, and verification tasks
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification skills
ExperienceTypically 8+ years in ASIC design, with leadership experienceUsually 2-5 years in ASIC design roles
Work EnvironmentDesign teams, project planning, cross-functional collaborationDesign labs, simulation environments, coding and testing

The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.

What are the key skills and qualifications needed to thrive as an ASIC Design Manager, and why are they important?

To thrive as an ASIC Design Manager, you need expertise in digital and analog ASIC design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), verification methodologies, and knowledge of relevant design flows is crucial. Strong leadership, communication, and problem-solving skills help manage teams and coordinate with cross-functional stakeholders. These competencies ensure high-quality chip designs are delivered on time and meet performance and cost targets, which is vital for organizational success.

What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?

ASIC Design Managers often navigate the complexities of coordinating multidisciplinary teams, including digital, analog, verification, and physical design engineers. One common challenge is ensuring clear communication across these specialties to maintain alignment on project goals, timelines, and technical requirements. Additionally, managing shifting priorities, resolving technical bottlenecks, and balancing resource allocation are frequent hurdles. Successful managers foster collaboration, set clear expectations, and leverage structured project management practices to keep teams productive and motivated.

What does an ASIC Design Manager do?

An ASIC Design Manager oversees the design and development of Application Specific Integrated Circuits (ASICs), managing a team of engineers through the entire chip design process. They coordinate project timelines, ensure technical specifications are met, and facilitate communication between design, verification, and manufacturing teams. Their role also involves resource planning, risk management, and ensuring that the final product meets performance, cost, and quality targets.
What are the most commonly searched types of Asic Design jobs in Washington? The most popular types of Asic Design jobs in Washington are:
What are popular job titles related to Asic Design Manager jobs in Washington? For Asic Design Manager jobs in Washington, the most frequently searched job titles are:
What job categories do people searching Asic Design Manager jobs in Washington look for? The top searched job categories for Asic Design Manager jobs in Washington are:
Asic Design Manager jobs near you
Infographic showing various Asic Design Manager job openings in Washington as of July 2026, with employment types broken down into 20% As Needed, 68% Full Time, 9% Part Time, 2% Contract, and 1% Summer. Highlights an 85% Physical, 9% Hybrid, and 6% Remote job distribution, with an average salary of $129,672 per year, or $62.3 per hour.
FPGA/ASIC Design Engineer

FPGA/ASIC Design Engineer

3B Staffing LLC

Reston, VA • On-site

$128K - $176K/yr

Full-time

This job post has expired today. Applications are no longer accepted.

Job description

Job Category: Technicall/Professional Job Description: Reporting to the Manager, Engineering (ASIC/FPGA), the Design Engineer will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols. L3Harris has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS). This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security. Skills/Experience: Bachelors Degree in Electrical Engineering or equivalent degree, and minimum 4 years of prior relevant experience (or Masters Degree plus 2 years of prior relevant experience) developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products. Possess an active SECRET Clearance Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs. Proficient in VHDL design process and FPGA flow Knowledge of Ethernet, TCP/IP protocols Strong logic/board debug, and analytical skills. Excellent written, verbal, and presentation skills. A PLUS for prior experience with: High Level Synthesis (HLS) with Vivado, Embedded SW C++ (OOP) and System Verilog Assertions (SVA) Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet) VHDL Experience is required for all candidates to be considered.
  • Looking for mid-senior level folks
  • Proficient in VHDL >5 yrs, Xilinx FPGA design EDA- Vivado
  • Must have done hands on multiple complex designs arch/design/verification/Synthesis/STA
  • Big Plus
    • Working with Ethernet protocol (not just instantiating the IP) Is a big plus.
    • Mentor EDA CDC/Lint/AC/RDC
Required Skills: Derive engineering specifications from system requirements and develop detailed architecture Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint) Generate test plans Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards Silicon/FPGA bring up, characterization and production ramp/support/collateral Desired Skills: Prior experience in Aerospace / Defense Experience in C++ (OOP) Experience in Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS. Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto). Experience with Universal Verification Mythology (UVM) Experience with project leadership and EVM Degree Requirements: Bachelors Degree in Electrical Engineering or equivalent degree, and minimum 4 years of prior relevant experience (or Masters Degree plus 2 years of prior relevant experience) developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products. MUST HAVE AN ACTIVE SECRET

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