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Asic Design Engineers Working Jobs (NOW HIRING)

We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...

We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...

We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...

Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication ... The responsibility includes working with system engineering or product marketing department to ...

Senior ASIC Design Engineer Description - HP is the world's leading printing company. We are ... This location brings together talented engineers working on next-generation technologies that power ...

Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication ... The responsibility includes working with system engineering or product marketing department to ...

Engineers in this role may work on different aspects of ASIC and SoC development, including architecture, RTL design, implementation, timing analysis, design methodology, automation, and siliconbring ...

Engineers in this role may work on different aspects of ASIC and SoC development, including architecture, RTL design, implementation, timing analysis, design methodology, automation, and silicon ...

ASIC Design Engineer

Santa Clara, CA · On-site

$156K - $165K/yr

ASIC Design Engineer Design, implement and debug the complex secure crypto engine SOC (System on ... systems engineers to ensure smooth interface of the SOC (System on Chips). Req. MSEE/CE/CS. Pay ...

NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading GPU and SoC's. With the System-ASIC team, you will contribute to designing multiple products that ...

Engineers in this role may work on different aspects of ASIC and SoC development, including architecture, RTL design, implementation, timing analysis, design methodology, automation, and silicon ...

NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading GPU and SoC's. With the System-ASIC team, you will contribute to designing multiple products that ...

NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading GPU and SoC's. With the System-ASIC team, you will contribute to designing multiple products that ...

NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... We have some of the most forward-thinking and hardworking people in the world working for us. If ...

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Asic Design Engineers Working information

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$94K

$150.2K

$202K

How much do asic design engineers working jobs pay per year?

As of Sep 11, 2026, the average yearly pay for asic design engineers working in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What are popular job titles related to Asic Design Engineers Working jobs?

For Asic Design Engineers Working jobs, the most frequently searched job titles are:

ASIC Design Engineer

San Francisco, CA • On-site

Other

Re-posted 2 days ago


Job description

We’re looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer.

Ideal Background:
  • Hands-on experience with multiple advanced node tapeouts
  • Ownership of ASIC design portion of at least one block in multiple advanced node tapeouts
  • Understanding of PPA improvement and what levers exist for each level of the stack
  • Ability to think creatively about methodology for fast design iterations
Nice to Have:
  • Hands-on experience with ASIC design process for large die (ideally reticle max) chips
  • Hands-on experience with ASIC design process for AI chips
  • Hands-on experience with multi-die/multi-chiplet/MCM designs
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