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Ai Chip Design Rtl Jobs in Simpsonville, SC (NOW HIRING)

AERONIX INC

Senior FPGA Design Engineer

Greenville, SC · On-site

$145K - $175K/yr

Lead full life-cycle FPGA development, from requirements and architecture through RTL ... Experience with System-on-Chip technologies. PREFERRED SKILLS * Proficiency in FPGA Block Design ...

AERONIX INC

Senior FPGA Design Engineer

Greenville, SC · On-site

$145K - $175K/yr

Lead full life-cycle FPGA development, from requirements and architecture through RTL ... Experience with System-on-Chip technologies. PREFERRED SKILLS * Proficiency in FPGA Block Design ...

All JobsAi Chip Design Rtl JobsAi Chip Design Rtl Jobs in Simpsonville, SC

Ai Chip Design Rtl information

See Simpsonville, SC salary details

$71.3K

$123.5K

$161.7K

How much do ai chip design rtl jobs pay per year?

As of Aug 7, 2026, the average yearly pay for ai chip design rtl in Simpsonville, SC is $123,519.00, according to ZipRecruiter salary data. Most workers in this role earn between $120,500.00 and $120,500.00 per year, depending on experience, location, and employer.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.
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Ai Chip Design Rtl jobs near you
Infographic showing various Ai Chip Design Rtl job openings in Simpsonville, SC as of August 2026, with employment types broken down into 1% Internship, 85% Full Time, 9% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $123,519 per year, or $59.4 per hour.

Senior FPGA Design Engineer

AERONIX INC

Greenville, SC • On-site

$145K - $175K/yr

Full-time

Posted 16 days ago

Job description


Job Title: Senior FPGA Engineer
Department: Engineering
Reports To: Functional Team Lead / Program Manager
FLSA Status: Exempt / Full-time

Salary Range: $145k - $175k Annually

DoD Secret clearance (or higher) REQUIRED.


ROLE

We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop the architecture, implementation, and verification of complex, high-speed FPGA solutions. The ideal candidate will have deep expertise in high-bandwidth interfaces such as PCIe Gen4/5, 10 to 100G+ Ethernet, and DDR4/DDR5, along with strong skills in RTL design (VHDL/Verilog/ SystemVerilog), timing closure, and signal integrity. Experience with Cryptography, DSP and RF applications is strong plus. This role involves driving FPGA design from concept through production, integrating vendor IP, optimizing for low latency and high throughput, and performing rigorous verification and lab validation. The engineer will collaborate across hardware and software teams, mentor junior engineers, and ensure designs meet stringent reliability and compliance standards.

RESPONSIBILITIES

  • Lead full life-cycle FPGA development, from requirements and architecture through RTL implementation (Verilog/VHDL), verification, and system integration across multiple FPGA families.
  • Define and document FPGA architecture, including block diagrams, clocking strategies, and trade-off analyses; participate in and conduct design reviews.
  • Develop robust, reusable, and self-checking testbenches; implement functional coverage models and achieve code coverage closure.
  • Create and execute detailed test plans, procedures, and reports; ensure verification rigor and traceability.
  • Collaborate with hardware and software teams to integrate FPGA designs at the board and system level; support lab bring-up, debug, and qualification testing.
  • Implement and validate JTAG boundary scan and other DFT features; ensure compliance with design-for-test and reliability standards.
  • Drive continuous improvement in design practices, coding standards, and verification methodologies; mentor junior engineers and contribute to technical reviews.

REQUIRED SKILLS

  • Strong proficiency in RTL design using Verilog/VHDL, including custom implementations beyond vendor IP integration.
  • Strong experience in testbench development, functional coverage, and verification of complex FPGA designs.
  • Proficient with FPGA simulation and synthesis tools (e.g., QuestaSim, ModelSim, Riviera-PRO, Xilinx Vivado, Intel Quartus).
  • Proficiency of FPGA architecture and optimization techniques for timing closure, floor-planning, and resource utilization.
  • Ability to perform FPGA power estimation and analysis using vendor tools and optimize designs for power and thermal constraints.
  • Strong understanding of high-speed interfaces (PCIe, Ethernet, Serial RapidIO, DDRx) and control protocols (I²C, SPI, RS-232/422).
  • Experience with System-on-Chip technologies.

PREFERRED SKILLS

  • Proficiency in FPGA Block Design development and debugging (e.g., Vivado, Libero).
  • Familiarity with Universal Verification Methodology (UVM).
  • Familiarity with Microsemi Libero and Lattus Diamond.
  • Familiarity with revision control systems (Git/Bitbucket) and scripting in Python, TCL, or Linux shell for automation.
  • Skilled in FPGA lab validation using oscilloscopes, logic analyzers, and protocol analyzers.
  • Support JTAG Boundary scan design and testing
  • Experience with Cryptography, Digital Signal Processing and RF Applications
  • MATLAB modeling
  • Strong oral and written communication skills, with ability to document and present technical work clearly.
  • Experience collaborating in Agile environments and using tools like Jira and requirements management systems (e.g., Jama).
  • Familiarity with Manufacturing processes, and Electronic Stress Screening.
  • Understanding of formal verification processes and compliance standards.

QUALIFICATIONS

  • Bachelor’s Degree in Electrical Engineering, Computer Engineering, or related field.
  • Minimum 10 years of relevant experience in FPGA design.
  • Excellent written and verbal communication skills.
  • Ability to work in a collaborative team environment.
  • DoD Secret clearance (or higher) REQUIRED.
  • Position located in Melbourne, FL or Greenville, SC (not remote).