... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
Custom Circuits Design Engineer
$150K - $277K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Custom Circuits Design Engineer
$150K - $277K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Custom Circuits Design Engineer
$150K - $277K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Custom Circuits Design Engineer
$150K - $277K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Prior SRAM, Coherent Cache or interconnect/NOC RTL design experience * Prior experience with ... or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or ...
Prior SRAM, Coherent Cache or interconnect/NOC RTL design experience * Prior experience with ... or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or ...
Postdoctoral Fellow - ECE Y. Zhang
Charlotte, NC · On-site
$60K/yr
D in Electrical Engineering, Physics or related areas awarded within the last five years. * SRAM design, fabrication, and testing: Expertise in all areas is highly preferred * Design, fabrication ...
Postdoctoral Fellow - ECE Y. Zhang
Charlotte, NC · On-site
$60K/yr
D in Electrical Engineering, Physics or related areas awarded within the last five years. * SRAM design, fabrication, and testing: Expertise in all areas is highly preferred * Design, fabrication ...
Work closely with other engineering teams, such as analog and digital, to ensure seamless ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Work closely with other engineering teams, such as analog and digital, to ensure seamless ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Work closely with other engineering teams, such as analog and digital, to ensure seamless ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Work closely with other engineering teams, such as analog and digital, to ensure seamless ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
Microprocessor VLSI Physical Design Engineer
Fort Collins, CO · On-site
$175K/yr
Knowledge of digital circuits, high speed flops, synchronizers, level shifters, and SRAM ... or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or ...
Microprocessor VLSI Physical Design Engineer
Fort Collins, CO · On-site
$175K/yr
Knowledge of digital circuits, high speed flops, synchronizers, level shifters, and SRAM ... or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or ...
Microprocessor VLSI Physical Design Engineer
Fort Collins, CO · Hybrid
$134K - $138K/yr
Knowledge of digital circuits, high speed flops, synchronizers, level shifters, and SRAM ... or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or ...
Microprocessor VLSI Physical Design Engineer
Fort Collins, CO · Hybrid
$134K - $138K/yr
Knowledge of digital circuits, high speed flops, synchronizers, level shifters, and SRAM ... or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ... Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations:US ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ... Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations:US ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ... Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations:US ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ... Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations:US ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ... Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations:US ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ... Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations:US ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ... Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ... Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ... Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations:US ...
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ... Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations:US ...
VLSI RTL Design Engineer
Fort Collins, CO · On-site
$106K/yr
Prior SRAM, Coherent Cache or interconnect/NOC RTL design experience * Prior experience with ... or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or ...
VLSI RTL Design Engineer
Fort Collins, CO · On-site
$106K/yr
Prior SRAM, Coherent Cache or interconnect/NOC RTL design experience * Prior experience with ... or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or ...
Microprocessor VLSI Physical Design Engineer
Fort Collins, CO · On-site
$126K/yr
Knowledge of digital circuits, high speed flops, synchronizers, level shifters, and SRAM ... or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or ...
Microprocessor VLSI Physical Design Engineer
Fort Collins, CO · On-site
$126K/yr
Knowledge of digital circuits, high speed flops, synchronizers, level shifters, and SRAM ... or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or ...
CPU Cache Microarchitect/RTL Engineer
$150K - $277K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$150K - $277K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
3Rd Shift Sram Design Engineer information
See salary details
$40.5K - $51.2K
2% of jobs
$51.2K - $62K
11% of jobs
$67.7K is the 25th percentile. Wages below this are outliers.
$62K - $72.7K
23% of jobs
The median wage is $79.6K / yr.
$72.7K - $83.4K
22% of jobs
$83.4K - $94.1K
17% of jobs
$94.4K is the 75th percentile. Wages above this are outliers.
$94.1K - $104.9K
9% of jobs
$104.9K - $115.6K
6% of jobs
$115.6K - $126.3K
3% of jobs
$126.3K - $137K
3% of jobs
$137K - $147.8K
2% of jobs
$147.8K - $158.5K
1% of jobs
$40.5K
$88.2K
$158.5K
How much do 3rd shift sram design engineer jobs pay per year?
As of Jul 15, 2026, the average yearly pay for 3rd shift sram design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.
What are the most commonly searched types of Sram Design Engineer jobs? The most popular types of Sram Design Engineer jobs are:
Apple rating
8.1
Based on 670 frontline employees who took The Breakroom Quiz
5th of 30 rated technology retailers
Job description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!
Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer who can drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems.
Description
As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following:
• Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification
• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Experience with microprocessor architecture
Experience with logic design principles with timing and power implications
Experience in Verilog or VHDL
Experience with simulators and waveform debugging process
Preferred Qualifications
Expertise in one or more of the following areas: coherence protocols and interconnects, high performance (low latency, high bandwidth) design techniques, memory subsystem queuing, scheduling, starvation and deadlock avoidance, SRAM design basics, multiple clock/power domains and power management strategies, prefetchers, replacement policies, debug capabilities, DFT strategies, error detection and correction
Understanding of low power microarchitecture techniques
Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
Experience in C or C++ programming
Experience using an interpretive language such as Perl or Python
Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer who can drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems.
Description
As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following:
• Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification
• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Experience with microprocessor architecture
Experience with logic design principles with timing and power implications
Experience in Verilog or VHDL
Experience with simulators and waveform debugging process
Preferred Qualifications
Expertise in one or more of the following areas: coherence protocols and interconnects, high performance (low latency, high bandwidth) design techniques, memory subsystem queuing, scheduling, starvation and deadlock avoidance, SRAM design basics, multiple clock/power domains and power management strategies, prefetchers, replacement policies, debug capabilities, DFT strategies, error detection and correction
Understanding of low power microarchitecture techniques
Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
Experience in C or C++ programming
Experience using an interpretive language such as Perl or Python
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976