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We are seeking a SoC Architect to define and drive the architecture of next‑generation XPUs for AI Infrastructure. This role involves end‑to‑end ownership of system and SoC architecture, from concept to silicon, with a strong emphasis on scalability, performance, interconnects, and system‑level optimization.

Key Responsibilities

• Define system architecture for complex SoCs, including compute, interconnect, memory, and IO subsystems.
• Drive architecture for scalable and modular designs, including chiplet‑based systems (UCIe).
• Design memory subsystems (DDR, LPDDR, HBM).
• Collaborate with design and DV teams to ensure architectural feasibility and efficient implementation.
• Develop performance models and simulations to validate architecture choices.
• Drive trade‑offs across performance, power, area, and cost.
• Define system‑level verification and validation strategies.
• Work closely with customers and software teams to align architecture with real‑world workloads.
• Influence long‑term roadmap and technology direction.
• Leverage AI tools and agents to enhance engineering productivity, quality, and scalability.
• Partner with AI engineers to define, shape, and operationalize AI‑driven workflows for design, verification, analysis, and quality assurance.
• Drive adoption of AI‑enabled methodologies to improve efficiency, coverage, and time‑to‑silicon.

Required Qualifications

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 18+ years of experience in SoC or system architecture.
• Proven track record of architecting complex SoCs for AI, HPC, or networking.
• Deep understanding of system‑level design and trade‑offs.
• Expertise in high‑speed IO protocols (UCIe, PCIe, Ethernet).
• Experience with performance modeling and architectural simulation.
• Strong cross‑functional collaboration skills.

Preferred Qualifications

• Experience with memory architectures (DDR, HBM, cache hierarchies).
• Familiarity with chiplet architectures and advanced packaging (2.5D/3D).
• Knowledge of coherency protocols (CXL, CHI).
• Experience with power/performance optimization at the system level.
• Exposure to software‑hardware co‑design.

Key Attributes

• Strong system‑level thinking and architectural vision.
• Ability to balance innovation with practical execution.
• High ownership and accountability.
• Strong communication and leadership skills.

Success Metrics

• Scalable and efficient SoC architectures across multiple generations.
• Achievement of performance, power, and cost targets.
• Strong alignment between architecture and silicon outcomes.
• Reduced architectural rework through early validation.

Compensation

175,000 – 350,000 USD per year (San Jose, HQ).