PHY RTL Design Engineer
Irvine, CA · On-site
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols. Minimum Qualifications Bachelors degree in ...
Rdc
33 Rdc Jobs Hiring in Riverside, CA
PHY RTL Design Engineer
Irvine, CA · On-site
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols. Minimum Qualifications Bachelors degree in ...
PHY RTL Design Engineer
Irvine, CA · On-site
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols. Minimum Qualifications Bachelors degree in ...
PHY RTL Design Engineer
Irvine, CA · On-site
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols. Minimum Qualifications Bachelors degree in ...
PHY RTL Design Engineer
Irvine, CA · On-site
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols. Minimum Qualifications Bachelors degree +10 ...
PHY RTL Design Engineer
Irvine, CA · On-site
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols. Minimum Qualifications Bachelors degree +10 ...
PHY RTL Design Engineer
$122K - $214K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$122K - $214K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$122K - $214K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$122K - $214K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$122K - $214K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$122K - $214K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$175K - $308K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$175K - $308K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$175K - $308K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$175K - $308K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$122K - $214K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$122K - $214K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$122K - $214K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$122K - $214K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$122K - $214K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$122K - $214K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$175K - $308K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
PHY RTL Design Engineer
$175K - $308K/yr
Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification ...
Market Delivery Support Specialist
Moreno Valley, CA · On-site
$19.85 - $24.30/hr
... g., RDC, BDC), store operations, and service providers. • Foster strong relationships with Pro partners and vendors. • Demonstrate adaptability in a fast-paced environment with multiple ...
Market Delivery Support Specialist
Moreno Valley, CA · On-site
$19.85 - $24.30/hr
... g., RDC, BDC), store operations, and service providers. • Foster strong relationships with Pro partners and vendors. • Demonstrate adaptability in a fast-paced environment with multiple ...
Apple rating
8.1
Based on 670 frontline employees who took The Breakroom Quiz
5th of 30 rated technology retailers
Job description
Come join Apple's growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.
Description
Develop signal processing intensive design for wireless communication SoCs, including:
Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model. Architecting area and power. Efficient low latency designs with scalabilities and flexibilities. Work with algorithm and software team to ensure performance and power efficiency. Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.
Minimum Qualifications
Bachelors degree in related field.
Understanding of DSP fundamentals.
Digital Communications knowledge.
Proficiency in RTL Design.
Preferred Qualifications
Familiarity with UVM DV environment and AI based efficiency improvement flows.
Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications.
Understanding of Decoders - Viterbi, LDPC, Polar.
Understanding of Filter design, multi-radix implementation, and compromises.
Knowledgeable in modern design techniques and energy-efficient/low power logic design, and power analysis.
Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post-silicon power correlation.
Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP is a plus.
Background in computer architecture.
Bus fabric, especially APB/AHB/AXI.
Power management with multiple power domains.
Ability to work well in a team and be productive under ambitious schedules.
Should exhibit excellent interpersonal skills and be self-motivated and well-organized.
Experience with FPGA and/or emulation platform desired.
Excellent communication skills - both written, and oral.
Description
Develop signal processing intensive design for wireless communication SoCs, including:
Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model. Architecting area and power. Efficient low latency designs with scalabilities and flexibilities. Work with algorithm and software team to ensure performance and power efficiency. Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.
Minimum Qualifications
Bachelors degree in related field.
Understanding of DSP fundamentals.
Digital Communications knowledge.
Proficiency in RTL Design.
Preferred Qualifications
Familiarity with UVM DV environment and AI based efficiency improvement flows.
Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications.
Understanding of Decoders - Viterbi, LDPC, Polar.
Understanding of Filter design, multi-radix implementation, and compromises.
Knowledgeable in modern design techniques and energy-efficient/low power logic design, and power analysis.
Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post-silicon power correlation.
Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP is a plus.
Background in computer architecture.
Bus fabric, especially APB/AHB/AXI.
Power management with multiple power domains.
Ability to work well in a team and be productive under ambitious schedules.
Should exhibit excellent interpersonal skills and be self-motivated and well-organized.
Experience with FPGA and/or emulation platform desired.
Excellent communication skills - both written, and oral.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976