3 Itlearn360 Graphic Designer Jobs Hiring Near You

General Summary

Physical implementation of industry leading integrated graphics core designs from netlist to GDS of very complex and high frequency blocks or top level. This includes floor‑planning, placement, clock implementation and routing of very high gate count design to meet very aggressive Power, Performance and Area (PPA) targets. Involves working on latest technology process nodes and employing latest design techniques to push PPA envelope which includes working with RTL design teams to optimize design. Incumbent is also expected to be involved in collaboration with multi‑disciplined teams and tool vendors to develop/enhance automation in flows and methodologies for design efficiency improvement. This role requires understanding of trade‑offs to be made for PPA, hence decisions taken to get the optimal design.

Key Skills & Experience

• Experience in Physical design which includes floor‑planning, placement, clock implementation, routing for complex, high frequency designs
• Experience with physical synthesis and implementation tools – Synopsys Fusion Compiler, ICC2 and Cadence Genus/Innovus
• Must have good knowledge of static timing analysis, reliability and power analysis
• Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs
• Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks
• Strong understanding of GPU micro‑architecture and collaborate with RTL designers to improve bottlenecks for power and performance
• Solid working knowledge of scripting skills including Tcl, Perl or Python
• Excellent communication skills and collaboration in a team environment is a must

Preferred Skills

• Clock, power delivery network design, process technology, prior experience in flow and methodology development, block closure
• Hands‑on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff
• Hands‑on experience working with very complex designs that push the envelope of Power, Performance and Area
• Hands‑on experience working with sub‑micron technology process nodes e.g., 5nm, 4nm and below is highly advantageous
• Prior experience in flow and methodology development is an advantage
• RTL expertise (Verilog/System Verilog)
• Excellent debug and analytical skills
• Ability to work well in a collaborative environment with multi‑disciplined teams

Minimum Qualifications

• Bachelor’s degree in Electrical/Computer Engineering
• 10+ years of direct physical design work experience
• Strong background in VLSI design, scripting
• Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools
• Hands‑on experience taping out designs in sub‑micron technology node design < 10nm
• Expect strong self‑motivation and time management skills

Preferred Qualifications

• Master’s degree in Electrical/Computer Engineering
• 8+ years of direct physical design work experience
• In‑depth end‑to‑end experience from RTL2GDS, taping out at least 6 complex designs in deep sub‑micron technology node

Pay & Benefits

Pay range: $195,200.00 – $292,800.00. Competitive annual discretionary bonus program and opportunity for annual RSU grants. Highly competitive benefits package designed to support your success at work, at home, and at play.

Accessibility & EEO

If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑accomodations@qualcomm.com or call Qualcomm’s toll‑free number. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process.

Qualcomm is an equal‑opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.