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PHYSICAL DESIGN ENGINEER – PD Engineer

An outstanding, full-time opening has become available in the Silicon Valley, CA for a local individual with 4+ years of experience in ASIC Physical Design implementation. This position offers a competitive compensation package and the opportunity to work onsite with a highly collaborative semiconductor design team supporting advanced process technologies.

All candidates MUST have the following experiences to qualify for consideration

• DO NOT APPLY unless you have 4+ years of ASIC physical design experience (floorplanning, placement, CTS, and/or STA) – MUST
• Physical design implementation in advanced technology nodes (28nm and below) – MUST
• Timing closure & STA tools experience – MUST
• Clock tree synthesis (CTS), power grid design, & low-power implementation experience – REQUIRED
• Signal integrity & timing closure issues (OCV/AOCV/Statistical Timing) – REQUIRED
• Physical verification, IR drop analysis, Conformal Low Power (CLP), formal verification – HIGHLY PREFERRED
• Scripting experience (Tcl and/or Perl, C a plus) – REQUIRED
• Bachelor’s Degree in Electrical Engineering or related field is REQUIRED
• Candidates must be able to work onsite 5 days per week in the South Bay Area

If interested and QUALIFIED, please send resume in Microsoft Word format to: krissid@etechhi.com 

Etech Hi, Inc. is an equal opportunity employer/staffing firm and we are committed to providing a workplace free from harassment and discrimination. We celebrate the unique differences of our employees and candidates because that is what drives curiosity, innovation, and the success of our business. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, gender identity or expression, age, marital status, veteran status, disability status, pregnancy, parental status, genetic information, political affiliation, or any other status protected by the laws or regulations in the locations where we operate.

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