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60 Conductor Jobs Hiring Near You

Lead Architect

Austin, TX · On-site

$230 - $360/hr

We're looking for a lead architect to own a large portion of the system architecture of the A-0 and A-1 products. Ideal Background: An ideal candidate will have: * Experience leading the architecture ...

New

Architect- Subsystem

Austin, TX · On-site

$180 - $260/hr

We're looking for architects to own key blocks on the A-0 and A-1 systems. This is a role with ownership of an entire sub-block, and you will need to understand how it fits into the entire system and ...

ASIC Design Engineer

San Francisco, CA · On-site

$130 - $210/hr

We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...

Link Validation Engineer

Austin, TX · On-site

$110 - $160/hr

We're looking for link validation engineers to help with DVT and bringup of the core optical link and PHY. Ideal Background: Ideal candidates for this role should have: * Hands-on experience with the ...

New

Director, Design Verification - Samsung Semiconductor TheDRAM Development Lab (DDL) within Samsung's Memory Business Unit is focused on cutting‑edge memory and storage solutions for cloud and data ...

Network Architect

Boston, MA · On-site

$180 - $240/hr

We're looking for an architect to lead the design and implementation of the inter-wafer scale-up network. Connecting very high bandwidth and high capacity wafers into a "super-system" will enable ...

Physical Design Engineer

Austin, TX · On-site

$130 - $170/hr

We're looking for physical design engineers to help manage and execute the physical design process for the various dies that comprise our A-0 and A-1 systems. This will involve deciding what to do in ...

We're looking for memory subsystem architects to contribute and own aspects of the memory subsystem for the largest and highest bandwidth memory system ever built to date. This includes the ...

IO Module Engineer

Boston, MA · On-site

$90 - $130/hr

We're looking for engineers to contribute to the thermomechanical, electrical and mechanical design and assembly of the IO modules that attach to our A-0 and A-1 wafers. Ideal Background: * Deep ...

New

Staff Engineer, Compiler

San Jose, CA · On-site

$163 - $253/hr

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World ...

New

Link Validation Engineer

Boston, MA · On-site

$110 - $160/hr

We're looking for link validation engineers to help with DVT and bringup of the core optical link and PHY. Ideal Background: Ideal candidates for this role should have: * Hands-on experience with the ...

New

Verification Engineer/Lead

Boston, MA · On-site

$120 - $170/hr

We're looking for verification engineers to contribute to and own blocks, sub-systems and potentially the entire wafer-level and cluster-level verification. Ideal Background: Ideal candidates will ...

New

We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip). This spans bump ...

New

Lead Architect

San Francisco, CA · On-site

$230 - $360/hr

We're looking for a lead architect to own a large portion of the system architecture of the A-0 and A-1 products. Ideal Background: An ideal candidate will have: * Experience leading the architecture ...

New

IO Module Engineer

San Francisco, CA · On-site

$90 - $130/hr

We're looking for engineers to contribute to the thermomechanical, electrical and mechanical design and assembly of the IO modules that attach to our A-0 and A-1 wafers. Ideal Background: * Deep ...

New

Showing results 41-60

Lead Architect

Conductor

Austin, TX • On-site

$230 - $360/hr

Other

Posted 2 days ago

New


Job description

We’re looking for a lead architect to own a large portion of the system architecture of the A-0 and A-1 products.

Ideal Background:

An ideal candidate will have:

  • Experience leading the architecture of an entire system or subsystem (eg chip, board, die, package)
  • Deep understanding of AI workloads like LLM inference at workload levels and its system level implications
  • Experience with large multicore architectures

Nice to Have:

  • Experience with physical design process of large-die area, advanced node chips
  • Experience with multi-die designs such as MCMs and interposer designs
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