Digital Implementation AE Architect
$157K - $292K/yr
Overview The Architect will serve as a technical leader within Cadence's North America Field ... Prior experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Conformal, Cerebrus) and ...

$157K - $292K/yr
Overview The Architect will serve as a technical leader within Cadence's North America Field ... Prior experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Conformal, Cerebrus) and ...
$157K - $292K/yr
Overview The Architect will serve as a technical leader within Cadence's North America Field ... Prior experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Conformal, Cerebrus) and ...
Palo Alto, CA · On-site
$237K - $296K/yr
In this role, you will bridge the gap between System-on-Chip (SoC) design, power architecture ... Ansys HFSS, SIwave, Cadence Sigrity/Voltus-Fi, or Keysight ADS. Circuit & PDN Simulation: HSPICE ...
Palo Alto, CA · On-site
$237K - $296K/yr
In this role, you will bridge the gap between System-on-Chip (SoC) design, power architecture ... Ansys HFSS, SIwave, Cadence Sigrity/Voltus-Fi, or Keysight ADS. Circuit & PDN Simulation: HSPICE ...
Palo Alto, CA · On-site
$186K - $296K/yr
In this role, you will bridge the gap between System-on-Chip (SoC) design, power architecture ... Ansys HFSS, SIwave, Cadence Sigrity/Voltus-Fi, or Keysight ADS. * Circuit & PDN Simulation: HSPICE ...
Palo Alto, CA · On-site
$186K - $296K/yr
In this role, you will bridge the gap between System-on-Chip (SoC) design, power architecture ... Ansys HFSS, SIwave, Cadence Sigrity/Voltus-Fi, or Keysight ADS. * Circuit & PDN Simulation: HSPICE ...
Palo Alto, CA · On-site
$186K - $296K/yr
In this role, you will bridge the gap between System-on-Chip (SoC) design, power architecture ... Ansys HFSS, SIwave, Cadence Sigrity/Voltus-Fi, or Keysight ADS. * Circuit & PDN Simulation: HSPICE ...
Palo Alto, CA · On-site
$186K - $296K/yr
In this role, you will bridge the gap between System-on-Chip (SoC) design, power architecture ... Ansys HFSS, SIwave, Cadence Sigrity/Voltus-Fi, or Keysight ADS. * Circuit & PDN Simulation: HSPICE ...
San Jose, CA · On-site
$157K - $292K/yr
Overview The Architect will serve as a technical leader within Cadence's North America Field ... Prior experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Conformal, Cerebrus) and ...
San Jose, CA · On-site
$157K - $292K/yr
Overview The Architect will serve as a technical leader within Cadence's North America Field ... Prior experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Conformal, Cerebrus) and ...
$157K - $292K/yr
Overview The Architect will serve as a technical leader within Cadence's North America Field ... Prior experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Conformal, Cerebrus) and ...
$157K - $292K/yr
Overview The Architect will serve as a technical leader within Cadence's North America Field ... Prior experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Conformal, Cerebrus) and ...
San Jose, CA · On-site
$157K - $292K/yr
Overview The Architect will serve as a technical leader within Cadence's North America Field ... Prior experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Conformal, Cerebrus) and ...
San Jose, CA · On-site
$157K - $292K/yr
Overview The Architect will serve as a technical leader within Cadence's North America Field ... Prior experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Conformal, Cerebrus) and ...
$200K - $300K/yr
Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. * Design ... Partner with architects, logic designers, and analog design team for tapeout readiness. Key ...
Quick apply
$200K - $300K/yr
Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. * Design ... Partner with architects, logic designers, and analog design team for tapeout readiness. Key ...
$200K - $300K/yr
Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. * Design ... Partner with architects, logic designers, and analog design team for tapeout readiness. Key ...
Quick apply
$200K - $300K/yr
Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. * Design ... Partner with architects, logic designers, and analog design team for tapeout readiness. Key ...
San Jose, CA · On-site +1
$200K - $300K/yr
Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. • Design ... Partner with architects, logic designers, and analog design team for tapeout readiness. Key ...
San Jose, CA · On-site +1
$200K - $300K/yr
Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. • Design ... Partner with architects, logic designers, and analog design team for tapeout readiness. Key ...
Irvine, CA · On-site +1
$200K - $300K/yr
Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. • Design ... Partner with architects, logic designers, and analog design team for tapeout readiness. Key ...
Irvine, CA · On-site +1
$200K - $300K/yr
Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. • Design ... Partner with architects, logic designers, and analog design team for tapeout readiness. Key ...
$150K - $250K/yr
You will collaborate closely with architecture, RTL, circuit design, and verification teams to ... Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. Design ...
$150K - $250K/yr
You will collaborate closely with architecture, RTL, circuit design, and verification teams to ... Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. Design ...
$150K - $250K/yr
You will collaborate closely with architecture, RTL, circuit design, and verification teams to ... Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. Design ...
$150K - $250K/yr
You will collaborate closely with architecture, RTL, circuit design, and verification teams to ... Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. Design ...
... and architect comprehensive EM/SEB/thermal methodologies and drive deployment across multiple ... Voltus, Voltus-Fi, RedHawk-SC, Totem Hands-on experience with analysis, optimization, and debugging ...
... and architect comprehensive EM/SEB/thermal methodologies and drive deployment across multiple ... Voltus, Voltus-Fi, RedHawk-SC, Totem Hands-on experience with analysis, optimization, and debugging ...
San Jose, CA · On-site
$150K - $250K/yr
You will collaborate closely with architecture, RTL, circuit design, and verification teams to ... Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. • Design ...
San Jose, CA · On-site
$150K - $250K/yr
You will collaborate closely with architecture, RTL, circuit design, and verification teams to ... Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. • Design ...
Irvine, CA · On-site
$150K - $250K/yr
You will collaborate closely with architecture, RTL, circuit design, and verification teams to ... Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. • Design ...
Irvine, CA · On-site
$150K - $250K/yr
You will collaborate closely with architecture, RTL, circuit design, and verification teams to ... Own physical implementation of System-on-Chips (SoCs) or complex digital blocks. • Design ...
San Diego, CA · On-site
$144K - $148K/yr
... computer architecture, and/or digital systems. Preferred Qualifications Experience with industrial EDA backend tools including Redhawk, PrimeRail, Voltus. Experience with ASIC or AMS physical ...
San Diego, CA · On-site
$144K - $148K/yr
... computer architecture, and/or digital systems. Preferred Qualifications Experience with industrial EDA backend tools including Redhawk, PrimeRail, Voltus. Experience with ASIC or AMS physical ...
Austin, TX · On-site
$134K - $138K/yr
... computer architecture, and/or digital systems. Preferred Qualifications Experience with industrial EDA backend tools including Redhawk, PrimeRail, Voltus. Experience with ASIC or AMS physical ...
Austin, TX · On-site
$134K - $138K/yr
... computer architecture, and/or digital systems. Preferred Qualifications Experience with industrial EDA backend tools including Redhawk, PrimeRail, Voltus. Experience with ASIC or AMS physical ...
... systems deployed in AWS data centers. You'll collaborate deeply with power architecture, RTL design ... Voltus) and pre-silicon to post-silicon power model correlation - Experience with Machine Learning ...
... systems deployed in AWS data centers. You'll collaborate deeply with power architecture, RTL design ... Voltus) and pre-silicon to post-silicon power model correlation - Experience with Machine Learning ...
$184K - $324K/yr
... and architect comprehensive EM/SEB/thermal methodologies and drive deployment across multiple ... Voltus, Voltus-Fi, RedHawk-SC, Totem Hands-on experience with analysis, optimization, and debugging ...
$184K - $324K/yr
... and architect comprehensive EM/SEB/thermal methodologies and drive deployment across multiple ... Voltus, Voltus-Fi, RedHawk-SC, Totem Hands-on experience with analysis, optimization, and debugging ...
$157K - $292K/yr
Full-time
Medical, Dental, Vision, Retirement, PTO
Re-posted 14 days ago
9.0
Based on 5 frontline employees who took The Breakroom Quiz
34th of 247 rated software companies
Overview
The Architect will serve as a technical leader within Cadence's North America Field Applications Team, driving strategic customer engagements and influencing next-generation EDA & Agentic-AI solutions. This role demands exceptional technical depth, hands-on experience of design convergence, and the ability to align cross-functional teams toward delivering advanced design solutions for leading semiconductor companies.
Key Responsibilities
Technical Expertise: Lead technical engagements with customers and partners to achieve best-in-class PPA, working closely with design teams to meet customer success metrics, guiding adoption of Cadence's digital implementation, signoff technologies and AgenticAI features across advanced nodes (3nm and below).
Cross-Functional Collaboration: Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements.
Innovation & Enablement: Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for Synthesis, P&R, STA, IR Drop, and power/timing closure.
Thought Leadership: Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.
Qualifications
15+ years of experience in IC design implementation and signoff, with demonstrated success in managing large-scale technical programs.
BS/MS in Electrical Engineering, Computer Engineering, or related field.
Deep expertise in digital design fundamentals, advanced node implementation (3nm and below), and EDA tool ecosystems.
Proven track record of leading technical teams and driving customer success at executive levels.
Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure.
Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders.
Prior experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Conformal, Cerebrus) and competitive solutions highly desirable.
The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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Software development
5,001 - 10,000 Employees
San Jose, CA, US
1988