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60 Vkore Solutions Jobs Hiring Near You

Vkore Solutions

Lead ASIC DFT Engineer

San Jose, CA · On-site

... DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon ...

Vkore Solutions

Electrical Engineer

Houston, TX · On-site

Houston, Texas (Onsite) Role Purpose To own electrical engineering decisions for fully integrated modular solutions involving medium voltage, low voltage systems, switchgear, relay panels, MCCs, UPS ...

Vkore Solutions

Manufacturing Engineer

Pittsburgh, PA · On-site

$70K - $91K/yr

Hands-on shop-floor mindset with the ability to translate engineering requirements into practical production solutions. * Ability to manage complex, cross-functional manufacturing issues from ...

Vkore Solutions

Hardware Engineer 5

Longmont, CO · On-site

$122K - $161K/yr

The candidate should have HW development testing, where the design is being validated. Performs design and development engineering assignments related to hardware products and systems including ...

Vkore Solutions

Mechanical Designer

Wixom, MI · On-site

All Visas Work for this role and No BGV Required Minium 4 years Role: Mechanical Designer Location: Wixom, MI ( Onsite) Additional Details: We are looking for another mid to senior level Mechanical ...

Vkore Solutions

SAP SD Vistex Consultant

Fremont, CA · On-site

Drive systems-related project execution in direct partnership with business teams and extended development teams; document business results achieved through solution implementation * Project/Process ...

Vkore Solutions

Mechanical Engineer

Maple Grove, MN · On-site

Create engineering solutions for sheet metal design optimization * Participate and/or lead Continuous Improvement efforts * Support sales team with design review to ensure successful installation ...

Vkore Solutions

Oracle CRM Lead

San Jose, CA · On-site

Job expectation : * Lead onsite CRM initiatives involving Oracle Service Cloud configuration, customization, and integration with Genesys Cloud CX. * Serve as the primary liaison between business ...

Vkore Solutions

Data Center Technician

Plano, TX · On-site

Overview: We are seeking a dedicated and proactive Data Center Technician to join our team. This role primarily involves troubleshooting downed servers and collaborating with vendors for support ...

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Infographic showing various job openings at Vkore Solutions in the United States as of August 2026, with employment types broken down into 100% Contract. Highlights an 100% Physical job distribution.

Lead ASIC DFT Engineer

Vkore Solutions

San Jose, CA • On-site

Contractor

Re-posted 4 days ago

Job description

Role: Lead ASIC DFT Engineer

Location: Remote

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.