ZipRecruiter

Log In

Velaura

60 jobs near Columbus, OH

Velaura

Principal Packaging Engineer

Austin, TX · On-site

$200K - $300K/yr

Help define Velaura's long-term packaging roadmap as future products evolve. Required Qualifications Deep experience developing advanced semiconductor packages for high-performance SoCs. Strong ...

Velaura

Robotics & Autonomy Systems Architect

Boston, MA · On-site

$200K - $500K/yr

Your work will guide how Velaura's compute platforms support emerging applications in robotics, drones, and embodied AI. This role requires strong systems-level thinking, with the ability to ...

Velaura

RTL Power Engineer

Santa Clara, CA · On-site

$200K - $350K/yr

Role Overview We are looking for talented RTL Engineers to help build Velaura's next generation Physical AI SoC. You will work closely with architects, performance modelers, software engineers ...

Velaura

Design Verification Engineer

Austin, TX · On-site

$75K - $275K/yr

Role Overview We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next-generation Physical AI SoC. In this role, you will work closely with architects, RTL ...

Velaura

Senior Design Verification Engineer

Santa Clara, CA · On-site

$200K - $300K/yr

Role Overview We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next-generation Physical AI SoC. In this role, you will work closely with architects, RTL ...

Velaura

Senior Design Verification Engineer

Santa Clara, CA · On-site

$200K - $300K/yr

Role Overview We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next-generation Physical AI SoC. In this role, you will work closely with architects, RTL ...

Velaura

Principal Packaging Engineer

Austin, TX · On-site

$200K - $500K/yr

Role Overview We are looking for a Principal Packaging Engineer to own package architecture and development for Velaura's next-generation SoCs. This role will lead packaging from concept through ...

Velaura

Principal Packaging Engineer

Santa Clara, CA · On-site

$200K - $300K/yr

Help define Velaura's long-term packaging roadmap as future products evolve. Required Qualifications Deep experience developing advanced semiconductor packages for high-performance SoCs. Strong ...

Velaura

Senior Emulation Engineer

Santa Clara, CA · On-site

$200K - $500K/yr

Set up, own, and maintain emulation flows for the Velaura SoC on Palladium, Veloce, and/or Zebu. * Bring up designs on the emulator, resolving compile/elaboration, capacity/partitioning, and design ...

Velaura

RTL Power Engineer

Santa Clara, CA · On-site

$200K - $300K/yr

Role Overview We are looking for talented RTL Engineers to help build Velaura's next generation Physical AI SoC. You will work closely with architects, performance modelers, software engineers ...

Velaura

Functional Safety Architect

Santa Clara, CA · On-site

$200K - $300K/yr

Role Overview Velaura is designing the compute silicon that powers robots, autonomous systems, and intelligent machines that operate in the physical world-where a fault in the chip can translate ...

previous pagenext page

Showing results 21-40

Accelerator Compiler and Tool Chain Lead

Santa Clara, CA • On-site

Velaura
See more jobs at Velauraexternal

$200K - $300K/yr

Full-time

Medical, Dental, Vision, PTO

Re-posted 25 days ago

Job description

Role Overview
We are looking for an Accelerator Compiler Lead to own the compiler and model-lowering stack for Velaura's AI accelerator.This role will lead the path from customer AI models to optimized executable artifacts for our NPU, including graph import, operator lowering, compiler IR, graph transformations, quantization integration, code generation, graph partitioning, and compiler diagnostics. The ideal candidate has built or shipped compiler infrastructure for ML accelerators, GPUs, DSPs, or other heterogeneous compute targets.
Responsibilities

Lead architecture and development of the AI accelerator compiler stack.

Own model ingestion and graph lowering from frameworks and exchange formats such as PyTorch export flows, ONNX, TensorFlow Lite, or similar.

Define operator coverage strategy, lowering rules, graph transformations, fusion, partitioning, and fallback behavior.

Develop compiler optimization passes for tensor layout, tiling, memory movement, mixed precision, operator fusion, and hardware-specific scheduling.

Work closely with accelerator runtime and driver teams to define executable artifact formats, metadata, memory planning requirements, profiling hooks, and runtime constraints.

Partner with hardware architecture and NPU firmware teams on ISA, command streams, tensor layouts, data movement, hardware constraints, and compiler-visible performance features.

Own quantization compiler integration, including calibration metadata, precision selection, scale handling, layout constraints, and accuracy/performance tradeoffs.

Build compiler diagnostics that help customers understand unsupported operators, shape constraints, graph rewrites, quantization issues, and performance bottlenecks.

Establish compiler verification and regression strategy for graph transformations,IR lowering, numerical behavior, model accuracy, and performance.

Hire, mentor, and lead a team of compiler and ML systems engineers.

Required Qualifications

Deep experience with compiler development, ML graph compilers, or code generation for accelerators, GPUs, DSPs, or heterogeneous compute systems.

Strong understanding of ML model formats, graph IRs, operator lowering, tensor layouts, quantization, and runtime/compiler interfaces.

Strong C++ and Python programming skills and experience building production-quality compiler or systems software.

Experience with compiler frameworks or technologies such as MLIR, LLVM, TVM, XLA, IREE, Glow, TensorRT-like systems, OpenVINO-like systems, or equivalent.

Strong understanding of correctness risks in compiler optimizations, graph rewrites, mixed precision, operator fusion, and hardware-specific lowering.

Ability to work closely with hardware architects, firmware engineers, runtime engineers, model-integration teams, and SQA.

Experience leading technical teams or major architecture areas.

Preferred Qualifications

Experience with NPU, GPU, DSP, or AI accelerator compiler stacks.

Experience with quantization-aware compilation, mixed precision, sparsity, pruning, graph partitioning, or hardware-specific scheduling.

Experience supporting ONNX, PyTorch export, TensorFlow Lite, JAX/XLA,TorchDynamo/TorchInductor, or other model import flows.

Familiarity with robotics, computer vision, CNNs, transformers, detection, segmentation, depth, SLAM-adjacent perception, or edge AI workloads.

Experience building customer-facing compiler diagnostics and model-porting tools.

Experience with model-zoo release processes, accuracy validation, and reproducible benchmark artifacts.

Open-source compiler contributions or experience working with external framework communities.

$200,000 - $300,000 a year
Compensation & Benefits

At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a competitive base salary, performance-based incentives, and equity participation, allowing team members to share in the company's long-term success.

Your base pay will depend on your skills, qualifications, experience, and location.

In addition to compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well-being and growth of our team.

Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.

Why Velaura?

Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment
opportunities to minorities, women, individuals with disabilities, and protected veterans.

Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: [email protected]. This contact
information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.
apply for this job

Apply