Analog/Mixed Signal Verilog Modeling Design Engineer
Irvine, CA · On-site
$216K/yr
Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package) * Familiar with analog circuits such as LDOs, TIAs, analog muxing, SARADC sample-and-hold (S/H), comparators ...
