Role Overview Join a dynamic team as a senior digital chip design and verification engineer, contributing to an AI evaluation program that focuses on cutting-edge silicon and chip-design workflows.
New
Saidgig
20 jobs near Columbus, OH
Role Overview Join a dynamic team as a senior digital chip design and verification engineer, contributing to an AI evaluation program that focuses on cutting-edge silicon and chip-design workflows.
New
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Role Overview Join a dynamic team as a senior digital chip design and verification engineer, contributing to an AI evaluation program that focuses on cutting-edge silicon and chip-design workflows.
New
Role Overview Join a dynamic team as a senior digital chip design and verification engineer, contributing to an AI evaluation program that focuses on cutting-edge silicon and chip-design workflows.
New
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In this role, you will leverage your Java expertise to contribute to the training of next-generation AI systems. Your efforts will directly influence how these models learn, reason, and perform by ...
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$100 - $135/hr
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Java Developer for AI Systems Training
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Python Developer for AI Model Training
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Physicist for AI Model Training
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Physicist for AI Model Training
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This role involves functioning as a research partner embedded within enterprise AI systems, focusing on improving system performance through real-world insights and experimental cycles. As a Member ...
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This role involves functioning as a research partner embedded within enterprise AI systems, focusing on improving system performance through real-world insights and experimental cycles. As a Member ...
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Full-time
This job post has expired today. Applications are no longer accepted.
Job description
Role Overview
Join a dynamic team as a senior digital chip design and verification engineer, contributing to an AI evaluation program that focuses on cutting-edge silicon and chip-design workflows. This role offers the opportunity to make a significant impact over the next few months, with a preference for candidates who can commit substantial time to the project.
Key ResponsibilitiesTwo parallel tracks are available for candidates to apply:
- Track 1: RTL Design Engineer
- Track 2: Design Verification Engineer
Track 1: RTL Design Engineer
- 3, 10 years of experience in digital RTL design
- Strong proficiency in Verilog / SystemVerilog
- Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols
- Experience with ASIC design flows: lint, synthesis, timing analysis, CDC, DFT-aware design
- Familiarity with common EDA tools for simulation, waveform debug, lint, CDC, synthesis, timing analysis
- Familiarity with leveraging LLM-based tools to accelerate chip design, RTL development, debug, documentation, or verification workflows
- Ability to write clear design documentation and communicate technical tradeoffs
- Experience debugging RTL issues using simulation logs and waveform viewers
- Strong collaboration skills across architecture, verification, and implementation teams
Preferred
- AMBA protocols (AXI, AHB, APB)
- Background in one or more of: CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect, low-power design
- Exposure to formal verification or SV/UVM-based design verification
Track 2: Design Verification Engineer
- 3, 10 years of experience in design verification
- Strong proficiency in SystemVerilog and UVM
- Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols
- Experience developing reusable verification components and testbench infrastructure
- Constrained-random verification, functional coverage, assertions (SVA), coverage closure
- Familiarity with EDA tools for simulation, waveform debug, coverage analysis, formal verification, regression management
- Familiarity with LLM-based tools to accelerate verification, debug, test generation, documentation, or coverage analysis
- Ability to write clear verification plans, debug reports, and technical documentation
Preferred
- AMBA protocols (AXI, AHB, APB)
- Background in one or more of: CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect, low-power verification
- Reusable verification IP, scoreboards, reference models, coverage-driven regression flows
Location: Remote, USA and Canada only
Commitment: Full-time preferred; high availability required (40 hours)
Duration: Target engagement of approximately 3+ months, starting the week of 04/23