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Greetings,

Position Title: Verification Engineer

Location: San Francisco Bay Area, CA

Employment Type: Contract

Required Skills & Qualification

Minimum 5 years of experience working of SV and UVM methodology.

Expertise in verif env development, functional coverage, code coverage, Testplan development, testcase writing,gate sims and debugging.

ÂExpertise in CXL (Compute express Link) is good to have

Expertise in IP as well as SOC verification

ÂPerl/shell scripting is a good to have

C/C++ knowledge is good to haveÂ

Any ONE item out of the following list is MUST / multiple skills out of following list will be preferred

Â1) Expertise in PCIe Gen3, Gen4 protocols is necessary

2) Expertise in SPI, JTAG, and Transceiver PHY is necessary

3) Expertise in Ethernet is necessary

Warm Regards,

Rahul

R3 Technology Inc.,

324 Courtyard Drive, Suite A

Hillsborough, New Jersey,Â08844

Direct:7328373458

Website: www.r3tek.com

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