Job Title: Senior Physical Design / STA Engineer - W2
$152.70K - $157.20K/yr
Experience with advanced technology nodes is preferred.
4 jobs near Columbus, OH
$152.70K - $157.20K/yr
Experience with advanced technology nodes is preferred.
$152.70K - $157.20K/yr
Experience with advanced technology nodes is preferred.
California City, CA · On-site
$166.80K - $171.70K/yr
Contribute to process technology migration and tool flow enhancements . Required Skills and Experience: * Strong expertise in digital ASIC/SoC physical design : floorplanning, placement, CTS, routing ...
California City, CA · On-site
$166.80K - $171.70K/yr
Contribute to process technology migration and tool flow enhancements . Required Skills and Experience: * Strong expertise in digital ASIC/SoC physical design : floorplanning, placement, CTS, routing ...
Direct Client Requirement : Drupal Developer - Westerville, OH (Onsite) Job Title: Drupal Developer ( / ) Location: Westerville, OH (Onsite) Duration: Long Term Responsibilities: Seeking a Drupal ...
New
Direct Client Requirement : Drupal Developer - Westerville, OH (Onsite) Job Title: Drupal Developer ( / ) Location: Westerville, OH (Onsite) Duration: Long Term Responsibilities: Seeking a Drupal ...
New
$67.50 - $87.25/hr
Role : Kinaxis Architect Location: Houston, TX (5 Days On-site) Kinaxis Role Overview We are seeking a Kinaxis Architect to lead the design and implementation of Kinaxis RapidResponse solutions for ...
$67.50 - $87.25/hr
Role : Kinaxis Architect Location: Houston, TX (5 Days On-site) Kinaxis Role Overview We are seeking a Kinaxis Architect to lead the design and implementation of Kinaxis RapidResponse solutions for ...
$152.70K - $157.20K/yr
Other
Posted 3 days ago
Location: Bay Area, CA / Austin, TX - CA 1st preference
Employment Type: Long-Term Contract (W2 Only)
We are seeking a Senior Physical Design / STA Engineer with strong hands-on experience in physical design and static timing analysis for advanced semiconductor projects. The ideal candidate will have expertise in timing closure, synthesis, place & route, and signoff activities for high-performance ASIC/SoC designs.