Kandou Bus Sa

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Kandou’s proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

We are actively seeking a System Architect based in US (Bay Area or Austin preferred), EU considered.

Responsibilities

• Own the SoC and Product Specification stack for a 1.6T retimer SoC and the AEC product it enables, at 224G/lane PAM4.
• Author and maintain normative specifications (SHALL/MUST/SHOULD/MAY language with REQ-ID traceability) that RTL, firmware, software, SI/PI, manufacturing, qualification, and customer engineering teams execute against.
• Standards scope spans IEEE 802.3ck/dj, OIF CEI-112G/224G, OSFP MSA, CMIS 5.x, EIA-364, JEDEC JESD22/51.
• Represent architecture in hyperscaler and strategic platform customer specification negotiation, including qualification test point, FEC telemetry, CMIS vendor-page, and thermal envelope commitments.

Requirements

• 12+ years in shipping high-speed interconnect (retimer, gearbox, PHY, AEC, AOC, coherent optics, SerDes-centric networking silicon).
• Prior System Architect, Chief Architect, or Principal Systems Engineer role on a shipping 100G/lane or higher product.
• Direct authorship of at least one product spec and one silicon spec on a shipping product.
• PAM4 link training, FEC, and on-die telemetry fluency at the specification level.
• Experience with DOORS / JAMA / equivalent traceability tooling.