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Work From Home Rtl Design Engineer Jobs in Hayward, CA

Purple Hires Inc

Lead ASIC DFT Engineer

San Jose, CA · Remote

Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

Meta

ASIC Engineer, Power

Sunnyvale, CA · On-site +1

$146K/yr

In this role, you will work at the intersection of EDA tooling, physical design, and power ... Collaborate with RTL design, physical design, and verification teams to identify and resolve power ...

Apple

Home Product Design Engineer

Sunnyvale, CA · On-site +1

$150K - $277K/yr

... work from concept through validation and into production. You will collaborate closely with cross ... Engineering, Industrial Design, Manufacturing Design, and more to ensure your designs meet ...

Cornelis Networks

PCIe ASIC Design Engineer

San Jose, CA · On-site +1

... work closely with board and firmware teams. * Debug functional and performance issues at RTL, gate ... Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or ...

Ashby

Design Engineer - Americas

San Francisco, CA · Remote

$126K - $250K/yr

... work, but also where I was seen as a rebel and an outsider. I want folks like me to feel at home at ... Our first hire was over five years ago, and we're doubling the team from five to over ten in the ...

MatX

Bluespec Design Engineer (Haskell)

Mountain View, CA · On-site +1

$175K - $362K/yr

Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ... All candidates must be authorized to work in the United States and work from our offices in ...

Atomic Machines

Generative AI CAD Engineer

Emeryville, CA · On-site +1

$210K - $260K/yr

This position is onsite in our Emeryville, CA office, with openness to an occasional work-from-home ... Design, Mechanical Engineering, Aerospace Engineering, Applied Math, or a related field. Recent ...

HMG Careers

Work From Home Sales Specialist

San Jose, CA · Remote

$69K/yr

Remote, work-from-home career * Average first-year earnings of $69K through commissions and bonuses * Increased earning potential in later years through performance and renewals * Residual income ...

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Showing results 21-40

All JobsRtl Design Engineer JobsWork From Home Rtl Design Engineer JobsWork From Home Rtl Design Engineer Jobs in Hayward, CA

Work From Home Rtl Design Engineer information

See Hayward, CA salary details

$46.4K

$101.1K

$181.7K

How much do work from home rtl design engineer jobs pay per year?

As of Aug 22, 2026, the average yearly pay for work from home rtl design engineer in Hayward, CA is $101,063.00, according to ZipRecruiter salary data. Most workers in this role earn between $78,000.00 and $112,900.00 per year, depending on experience, location, and employer.

What is a work from home RTL design engineer?

A Work From Home RTL (Register Transfer Level) Design Engineer is responsible for designing and implementing digital circuits using hardware description languages like Verilog or VHDL, all while working remotely. They develop RTL code for FPGA or ASIC designs, perform functional verification, and collaborate with hardware and software teams to ensure proper integration. This role requires strong knowledge of digital design principles, low-power design techniques, and simulation tools. Working remotely, engineers communicate via online tools, participate in virtual design reviews, and manage tasks independently while ensuring design quality and meeting project deadlines.

What are the key skills and qualifications needed to thrive as a work from home RTL design engineer?

A Work From Home RTL Design Engineer requires a thorough understanding of digital design, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard EDA tools like Synopsys, Cadence, or Mentor Graphics, and knowledge of design validation methodologies are commonly expected. Strong problem-solving abilities, effective communication skills, and self-motivation are crucial soft skills, particularly in a remote setting. These competencies ensure the engineer can deliver high-quality work, collaborate virtually with cross-functional teams, and meet project milestones in a distributed environment.

What are some typical challenges faced by work from home RTL design engineers, and how do companies support remote collaboration?

Remote RTL Design Engineers may face challenges such as limited access to on-site lab hardware, dependence on remote computing resources, and the need for clear communication across time zones. To address these, many companies provide secure VPN access, cloud-based EDA tool licenses, and regular virtual team meetings to ensure seamless project progress. You will often collaborate with verification, software, and hardware teams via video calls, shared documentation platforms, and version control systems. Structured onboarding, virtual mentorship programs, and flexible work hours are additional ways organizations support remote RTL designers. Adapting to these systems helps maintain productivity and fosters a collaborative team environment despite geographical distances.

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Work From Home Rtl Design Engineer jobs near you

Lead ASIC DFT Engineer

Purple Hires Inc

San Jose, CA • Remote

Contractor

Re-posted 6 days ago

Job description

Title - Lead ASIC DFT Engineer

Location – Remote (must be aligned with PST time zone)

 
Below is the detailed job description for your reference -
 

Job Description: 

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.