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Work From Home Rtl Design Engineer Jobs in Denton, TX

Purple Hires Inc

DFT Engineer

Plano, TX · Remote

Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

The Jernigan Agency

WORK FROM HOME

Plano, TX · On-site +1

$300 - $500/wk

We are looking for individuals interested in working from home, remotely, as life insurance sales representatives. We are hiring coachable individuals comfortable with a 100% commission based income ...

Purple Hires Inc

ASIC DFT Engineer

Plano, TX · Remote

Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

Purple Hires Inc

ASIC Engineer - Remote

Plano, TX · Remote

Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

AO Globe Life

Remote Work From Home Representative

Dallas, TX · On-site +1

$15.75 - $21.50/hr

Remote Work From Home Representative 100% Remote | Entry-Level Friendly | Full Training Provided | Flexible Schedule Looking for a remote opportunity where you can learn, grow, and build a long-term ...

Astura Medical

Sr. Design Engineer

Irving, TX · On-site +1

The Senior Design Engineer will be responsible for the design, development, verification and ... Normal work hours are from 8 am to 5 pm. Responsibilities * Primary leader of assigned product ...

HMG Careers

Work From Home Sales Specialist

Azle, TX · Remote

$69K/yr

Remote, work-from-home career * Average first-year earnings of $69K through commissions and bonuses * Increased earning potential in later years through performance and renewals * Residual income ...

HMG Careers

Work From Home Sales Specialist

Coppell, TX · Remote

$69K/yr

Remote, work-from-home career * Average first-year earnings of $69K through commissions and bonuses * Increased earning potential in later years through performance and renewals * Residual income ...

HMG Careers

Work From Home Sales Specialist

Ponder, TX · Remote

$69K/yr

Remote, work-from-home career * Average first-year earnings of $69K through commissions and bonuses * Increased earning potential in later years through performance and renewals * Residual income ...

HMG Careers

Work From Home Sales Specialist

Hurst, TX · Remote

$69K/yr

Remote, work-from-home career * Average first-year earnings of $69K through commissions and bonuses * Increased earning potential in later years through performance and renewals * Residual income ...

HMG Careers

Work From Home Sales Specialist

Azle, TX · Remote

$69K/yr

Remote, work-from-home career * Average first-year earnings of $69K through commissions and bonuses * Increased earning potential in later years through performance and renewals * Residual income ...

HMG Careers

Work From Home Sales Specialist

Corinth, TX · Remote

$69K/yr

Remote, work-from-home career * Average first-year earnings of $69K through commissions and bonuses * Increased earning potential in later years through performance and renewals * Residual income ...

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All JobsRtl Design Engineer JobsWork From Home Rtl Design Engineer JobsWork From Home Rtl Design Engineer Jobs in Denton, TX

Work From Home Rtl Design Engineer information

See Denton, TX salary details

$38K

$82.7K

$148.6K

How much do work from home rtl design engineer jobs pay per year?

As of Aug 12, 2026, the average yearly pay for work from home rtl design engineer in Denton, TX is $82,650.00, according to ZipRecruiter salary data. Most workers in this role earn between $63,800.00 and $92,400.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a work from home RTL design engineer?

A Work From Home RTL Design Engineer requires a thorough understanding of digital design, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard EDA tools like Synopsys, Cadence, or Mentor Graphics, and knowledge of design validation methodologies are commonly expected. Strong problem-solving abilities, effective communication skills, and self-motivation are crucial soft skills, particularly in a remote setting. These competencies ensure the engineer can deliver high-quality work, collaborate virtually with cross-functional teams, and meet project milestones in a distributed environment.

What is a work from home RTL design engineer?

A Work From Home RTL (Register Transfer Level) Design Engineer is responsible for designing and implementing digital circuits using hardware description languages like Verilog or VHDL, all while working remotely. They develop RTL code for FPGA or ASIC designs, perform functional verification, and collaborate with hardware and software teams to ensure proper integration. This role requires strong knowledge of digital design principles, low-power design techniques, and simulation tools. Working remotely, engineers communicate via online tools, participate in virtual design reviews, and manage tasks independently while ensuring design quality and meeting project deadlines.

What are some typical challenges faced by work from home RTL design engineers, and how do companies support remote collaboration?

Remote RTL Design Engineers may face challenges such as limited access to on-site lab hardware, dependence on remote computing resources, and the need for clear communication across time zones. To address these, many companies provide secure VPN access, cloud-based EDA tool licenses, and regular virtual team meetings to ensure seamless project progress. You will often collaborate with verification, software, and hardware teams via video calls, shared documentation platforms, and version control systems. Structured onboarding, virtual mentorship programs, and flexible work hours are additional ways organizations support remote RTL designers. Adapting to these systems helps maintain productivity and fosters a collaborative team environment despite geographical distances.

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What job categories do people searching Work From Home Rtl Design Engineer jobs in Denton, TX look for? The top searched job categories for Work From Home Rtl Design Engineer jobs in Denton, TX are:
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Work From Home Rtl Design Engineer jobs near you

DFT Engineer

Purple Hires Inc

Plano, TX • Remote

Contractor

Re-posted 13 days ago

Job description

Role: Lead ASIC DFT Engineer
Location: Remote, (Onsite)
Duration: Contract
 
Year of Exp: 8+ yrs to 15 yrs.
 
Job Description:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities:
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications:
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience:
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.