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Vlsi Physical Design Engineer Jobs in Raleigh, NC

Qorvo, Inc.

Staff Layout Design Engineer

Raleigh, NC

$144K - $187K/yr

Work closely with design engineers to ensure proper circuit performance * Design analog and RF ... on physical location) Posted salary ranges are made in good faith. Qorvo reserves the right to ...

Epstein

Electrical Design Engineer Co-Op

Raleigh, NC · On-site

$18 - $20/hr

Overview Epstein is offering a Co-Op Opportunity for an Electrical Design Engineer Intern seeking ... physical or mental disability, national origin, citizenship, veteran status, marital status ...

Analogdevices

Analog Design Engineer Intern

Durham, NC

$22 - $41/hr

ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable ... As an Analog Design Engineer Intern at Analog Devices (ADI), you will have the opportunity to work ...

Analog Devices

Digital Design Engineer Intern

Durham, NC · On-site

$19 - $35/hr

ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable ... As a Digital Design Engineer Intern at Analog Devices (ADI), you'll gain practical experience in ...

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Vlsi Physical Design Engineer information

See Raleigh, NC salary details

$92.3K

$137.5K

How much do vlsi physical design engineer jobs pay per year?

As of Sep 2, 2026, the average yearly pay for vlsi physical design engineer in Raleigh, NC is $135,509.00, according to ZipRecruiter salary data. Most workers in this role earn between $132,200.00 and $136,100.00 per year, depending on experience, location, and employer.

What is a VLSI physical design engineer?

A VLSI Physical Design Engineer is responsible for transforming digital circuit designs into a physical layout that can be manufactured on silicon. They work on placement, routing, clock tree synthesis, timing closure, power optimization, and design rule checks. Their role ensures that the design meets performance, power, and area requirements while complying with fabrication constraints.

What are the key skills and qualifications needed to thrive as a VLSI physical design engineer?

A VLSI Physical Design Engineer should have a strong background in electrical engineering, digital electronics, and deep knowledge of ASIC/FPGA design and physical design flow, generally supported by a relevant bachelor's or master's degree. Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting skills in TCL, Perl, or Python is crucial, and certifications in VLSI design are a plus. Excellent problem-solving abilities, communication skills, and the ability to collaborate effectively with cross-functional teams are important soft skills. These competencies ensure the engineer can manage complex design challenges, optimize chip performance, and deliver high-quality results in fast-paced semiconductor environments.

What are some typical challenges faced by VLSI physical design engineers, and how can I prepare for them?

VLSI Physical Design Engineers often encounter challenges such as managing tight timing constraints, optimizing power and area, and addressing design rule violations during the layout process. You may also need to troubleshoot tool-related issues or coordinate with logic, verification, and manufacturing teams to meet project milestones. To prepare, it's helpful to strengthen your understanding of physical verification, develop scripting skills for process automation, and stay current with the latest advancements in EDA tools. Being proactive in cross-team communication and problem-solving will help you address these challenges effectively and contribute to successful silicon tapeouts.

What are popular job titles related to Vlsi Physical Design Engineer jobs in Raleigh, NC?

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Vlsi Physical Design Engineer jobs near you
Infographic showing various Vlsi Physical Design Engineer job openings in Raleigh, NC as of August 2026, with employment types broken down into 1% As Needed, 81% Full Time, 14% Part Time, 3% Contract, and 1% Nights. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $124,266 per year, or $59.7 per hour.

Staff Layout Design Engineer

Qorvo, Inc.

Raleigh, NC

$144K - $187K/yr

Full-time

Posted 19 days ago

Qorvo rating

8.3

Company rating: 8.3 out of 10

Based on 21 frontline employees who took The Breakroom Quiz

Job description

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet.

In this position, you will work closely with design engineering groups to complete the layout and verification of high-performance Switches, Power Management Devices, and Integrated Products using Cadence Virtuoso XL and Mentor's Calibre tools.

Responsibilities

  • Work closely with design engineers to ensure proper circuit performance
  • Design analog and RF layout
  • Understand device matching techniques
  • Excellent teamwork skills, including written and verbal communications, with both local and remote design teams
  • Exceptional layout planning and integration skills from small block to full chip

Skills and Qualifications

  • Associates Degree in Electronic/IC layout CAD specialization or related program and 10+ years of IC layout experience
  • Ability to layout analog circuitry in a size/time constrained environment
  • Understand layout techniques such as common centroid, matching, isolation, and the use of dummy devices
  • Ability to solve design problems using technical skills, intuition, and creativity
  • Proficiency in floorplanning and assembly from block to full chip level
  • Working knowledge of Cadence and Mentor Verification tools
  • Strong LVS troubleshooting and debug skills
  • Demonstrated ability to work individually and in a team-orientated environment

Preferred Skills and Qualifications

  • BSEE/BS Engineering Technology or related program
  • Comfortable with CMOS and SOI technologies across multiple foundry PDKs
  • Demonstrated ability to contribute ideas for improved schematic and layout interaction
  • Schematic entry for dummy devices, resizing devices, and debugging LVS issues.

This position is not eligible for visa sponsorship by the Company.

Competitive base salary commensurate with experience: $144,300 - $187,600, relevant for the California Bay Area (subject to change dependent on physical location) 

Posted salary ranges are made in good faith. Qorvo reserves the right to adjust ranges depending on the experience/qualification of the selected candidate as well as external competitiveness and internal comparability. 

Base compensation is one element of Total Rewards offered at Qorvo. More information on the Total Rewards package can be shared upon request. 

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MAKE A DIFFERENCE AT QORVO   

 We are Qorvo. We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure markets - we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next. Explore the possibilities with us.

We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability. 

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