ZipRecruiter

Log In

1

Vlsi Intern Jobs in San Ramon, CA (NOW HIRING)

All JobsVlsi Intern JobsVlsi Intern Jobs in San Ramon, CA

Vlsi Intern information

See San Ramon, CA salary details

$9

$19

$27

How much do vlsi intern jobs pay per hour?

As of Aug 11, 2026, the average hourly pay for vlsi intern in San Ramon, CA is $19.04, according to ZipRecruiter salary data. Most workers in this role earn between $16.11 and $21.49 per hour, depending on experience, location, and employer.

What is a VLSI intern?

A VLSI Intern job involves working on Very Large Scale Integration (VLSI) design, verification, and testing processes. Interns assist in tasks such as designing digital and analog circuits, running simulations, debugging hardware, and optimizing semiconductor designs. They typically work with software tools like Cadence, Synopsys, or Mentor Graphics. This role helps interns gain hands-on experience in chip design and fabrication while collaborating with experienced engineers.

What are the key skills and qualifications needed to thrive in the VLSI intern position, and why are they important?

To thrive as a VLSI Intern, you need a strong background in digital and analog circuit design, semiconductor fundamentals, and hands-on experience with EDA tools such as Cadence or Synopsys, usually gained through coursework or lab projects in electrical or computer engineering. Familiarity with hardware description languages like Verilog or VHDL and version control systems is highly valued. Strong problem-solving skills, attention to detail, effective communication, and the ability to work collaboratively are important soft skills in this field. These competencies are crucial for delivering high-quality designs, working efficiently within chip design teams, and adapting to rapidly evolving project requirements.

What kind of projects or responsibilities can a VLSI intern expect during their internship?

As a VLSI Intern, you can expect to assist in various stages of the integrated circuit (IC) design process, including schematic entry, simulation, layout, and verification tasks under the guidance of experienced engineers. Interns often work on specific blocks or modules within larger chip projects, perform debugging, run testbenches, and help analyze results to improve design performance. You may also participate in team meetings, collaborate with cross-functional teams such as verification or design-for-test groups, and document your work for internal review. This hands-on experience is invaluable for understanding the full IC development lifecycle and gaining practical skills that can lead to full-time opportunities in the semiconductor industry.

What job categories do people searching Vlsi Intern jobs in San Ramon, CA look for? The top searched job categories for Vlsi Intern jobs in San Ramon, CA are:
What cities near San Ramon, CA are hiring for Vlsi Intern jobs? Cities near San Ramon, CA with the most Vlsi Intern job openings:
Vlsi Intern jobs near you

Physical Design Intern

SK hynix memory solutions America Inc.

San Jose, CA • On-site

$35 - $45/hr

Other

Re-posted 12 days ago

Job description

About the Company:

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change - we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

About the Role: Join our Physical Design team to help deliver next-generation SSD controller chips. As a Physical Design Intern, you will collaborate with experienced engineers to transform RTL designs into functional physical layouts. You will gain hands-on experience in the complete ASIC flow from synthesis to tape-out, working on real projects in a fast-paced, innovative environment.

Responsibilities:

  • Execute ASIC physical design implementation flows, including floorplanning, placement, clock tree synthesis (CTS), and routing.
  • Perform static timing analysis (STA) and work to resolve setup and hold timing violations.
  • Run and analyze design rule checks (DRC) and layout versus schematic (LVS) checks to ensure design integrity, as well as IR-Drop analysis.
  • Assist in optimizing power, performance, and area (PPA) metrics using industry-standard EDA tools.
  • Developing entire P&R/physical verification/IR-EM flows.
  • Collaborate with front-end design and verification teams to seamlessly integrate RTL changes and resolve physical design constraints.
  • Help generate and maintain physical design scripts, utilities, and documentation for the team.

Minimum Qualifications:

  • Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • Foundational understanding of VLSI design concepts, CMOS circuit design, and digital logic.
  • Familiarity with the basic stages of the ASIC physical design flow.
  • Academic or project experience with scripting languages such as Python, Perl, or TCL.
  • Strong analytical and problem-solving skills with a high attention to detail.

Preferred Qualifications:

  • Hands-on coursework or project experience with industry-standard EDA tools (e.g., Synopsys ICC2, Cadence Innovus, or similar).
  • Exposure to Static Timing Analysis (STA) concepts and tools (e.g., PrimeTime, Tempus).
  • Basic understanding of design constraints (SDC) and library exchange formats (LEF/DEF).
  • Knowledge of low-power design techniques and power intent formats (UPF/CPF).
  • Familiarity with AI/LLM tools (e.g., GPT, Copilot) and prompt engineering, with the ability to leverage them to automate EDA scripting, analyze design data, or optimize workflows.


COMPENSATION: $35/hr - $45/hr

Apply