Document architecture specifications; work with ASIC design, software, and VLSI teams to review and ... Experience with GPU architecture, especially in off-chip IO, memory subsystem, and/or Network-on ...
Document architecture specifications; work with ASIC design, software, and VLSI teams to review and ... Experience with GPU architecture, especially in off-chip IO, memory subsystem, and/or Network-on ...
2027 US Firmware Engineering Internship
Seattle, WA · On-site
$45/hr
Firmware Design and Development of AIoT infrastructure for career-defining new programs that ... Collaborate with System-on-Chip (SoC) and Cellular Modem vendors to optimize for AIoT use-cases and ...
2027 US Firmware Engineering Internship
Seattle, WA · On-site
$45/hr
Firmware Design and Development of AIoT infrastructure for career-defining new programs that ... Collaborate with System-on-Chip (SoC) and Cellular Modem vendors to optimize for AIoT use-cases and ...
Thermal Engineer, Satellites (Starlink)
$110K - $135K/yr
Experience with tools for chip thermal design like Flotherm or Icepak * 1+ years of experience using scientific programming languages (including internships) * Experience with Thermal Desktop and ...
Thermal Engineer, Satellites (Starlink)
$110K - $135K/yr
Experience with tools for chip thermal design like Flotherm or Icepak * 1+ years of experience using scientific programming languages (including internships) * Experience with Thermal Desktop and ...
Thermal Engineer, Satellites (Starlink)
Redmond, WA · On-site
$110K - $135K/yr
Experience with tools for chip thermal design like Flotherm or Icepak * 1+ years of experience using scientific programming languages (including internships) * Experience with Thermal Desktop and ...
Thermal Engineer, Satellites (Starlink)
Redmond, WA · On-site
$110K - $135K/yr
Experience with tools for chip thermal design like Flotherm or Icepak * 1+ years of experience using scientific programming languages (including internships) * Experience with Thermal Desktop and ...
Thermal Engineer, Satellites (Starlink)
Redmond, WA · On-site
$110K - $135K/yr
Experience with tools for chip thermal design like Flotherm or Icepak * 1+ years of experience using scientific programming languages (including internships) * Experience with Thermal Desktop and ...
Thermal Engineer, Satellites (Starlink)
Redmond, WA · On-site
$110K - $135K/yr
Experience with tools for chip thermal design like Flotherm or Icepak * 1+ years of experience using scientific programming languages (including internships) * Experience with Thermal Desktop and ...
Embedded Software Engineer, OS/Platform (Starlink)
Redmond, WA · On-site
$145K - $175K/yr
We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... Bringing up next generation space grade silicon, including in house designed system on chip and ...
Embedded Software Engineer, OS/Platform (Starlink)
Redmond, WA · On-site
$145K - $175K/yr
We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... Bringing up next generation space grade silicon, including in house designed system on chip and ...
OS/Platform Software Engineer (Starlink)
Redmond, WA · On-site
$145K - $175K/yr
We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... Bringing up next generation space grade silicon, including in house designed system on chip and ...
OS/Platform Software Engineer (Starlink)
Redmond, WA · On-site
$145K - $175K/yr
We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... Bringing up next generation space grade silicon, including in house designed system on chip and ...
Senior Machine Learning Compiler Engineer
Seattle, WA · On-site
$139K - $183K/yr
The Inferentia chip delivers best-in-class ML inference performance at the lowest cost in cloud ... The team covers multiple disciplines including silicon engineering, hardware design and ...
Senior Machine Learning Compiler Engineer
Seattle, WA · On-site
$139K - $183K/yr
The Inferentia chip delivers best-in-class ML inference performance at the lowest cost in cloud ... The team covers multiple disciplines including silicon engineering, hardware design and ...
Software Engineer- AI/ML, AWS Neuron Distributed Training - Performance Optimization
Seattle, WA · On-site
The Distributed Training team works side by side with chip architects, compiler engineers and ... non-internship design or architecture (design patterns, reliability and scaling) of new and ...
Software Engineer- AI/ML, AWS Neuron Distributed Training - Performance Optimization
Seattle, WA · On-site
The Distributed Training team works side by side with chip architects, compiler engineers and ... non-internship design or architecture (design patterns, reliability and scaling) of new and ...
Embedded Software Engineer, OS/Platform (Starlink)
Redmond, WA · On-site
$145K - $175K/yr
We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... Support in-house System on Chip and peripheral through the life-cycle of the part. * Support OS ...
Embedded Software Engineer, OS/Platform (Starlink)
Redmond, WA · On-site
$145K - $175K/yr
We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... Support in-house System on Chip and peripheral through the life-cycle of the part. * Support OS ...
Embedded Software Engineer, OS/Platform (Starlink)
Redmond, WA · On-site
$145K - $175K/yr
We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... Support in-house System on Chip and peripheral through the life-cycle of the part. * Support OS ...
Embedded Software Engineer, OS/Platform (Starlink)
Redmond, WA · On-site
$145K - $175K/yr
We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... Support in-house System on Chip and peripheral through the life-cycle of the part. * Support OS ...
OS/Platform Software Engineer (Starlink)
Redmond, WA · On-site
$145K - $175K/yr
We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... Support in-house System on Chip and peripheral through the life-cycle of the part. * Support OS ...
OS/Platform Software Engineer (Starlink)
Redmond, WA · On-site
$145K - $175K/yr
We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... Support in-house System on Chip and peripheral through the life-cycle of the part. * Support OS ...
OS/Platform Software Engineer (Starlink)
Redmond, WA · On-site
$145K - $175K/yr
We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... Support in-house System on Chip and peripheral through the life-cycle of the part. * Support OS ...
OS/Platform Software Engineer (Starlink)
Redmond, WA · On-site
$145K - $175K/yr
We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... Support in-house System on Chip and peripheral through the life-cycle of the part. * Support OS ...
Sr. Software Engineer- AI/ML, AWS Neuron Distributed Training - Performance Optimization
Seattle, WA · On-site
$139K - $183K/yr
The Distributed Training team works side by side with chip architects, compiler engineers and ... BASIC QUALIFICATIONS - - 5+ years of non-internship professional software development experience ...
Sr. Software Engineer- AI/ML, AWS Neuron Distributed Training - Performance Optimization
Seattle, WA · On-site
$139K - $183K/yr
The Distributed Training team works side by side with chip architects, compiler engineers and ... BASIC QUALIFICATIONS - - 5+ years of non-internship professional software development experience ...
Sr. Software Engineer- AI/ML, AWS Neuron Distributed Training
Seattle, WA · On-site
$139K - $183K/yr
The ML Distributed Training team works side by side with chip architects, compiler engineers and ... Our org covers multiple disciplines including silicon engineering, hardware design and verification ...
Sr. Software Engineer- AI/ML, AWS Neuron Distributed Training
Seattle, WA · On-site
$139K - $183K/yr
The ML Distributed Training team works side by side with chip architects, compiler engineers and ... Our org covers multiple disciplines including silicon engineering, hardware design and verification ...
Vlsi Chip Design Internship information
See Renton, WA salary details
$10.28 - $13.10
9% of jobs
$13.10 - $15.93
8% of jobs
$16.66 is the 25th percentile. Wages below this are outliers.
$15.93 - $18.76
28% of jobs
The median wage is $19.51 / hr.
$18.76 - $21.58
16% of jobs
$23.52 is the 75th percentile. Wages above this are outliers.
$21.58 - $24.41
20% of jobs
$24.41 - $27.24
9% of jobs
$27.24 - $30.06
4% of jobs
$30.06 - $32.89
1% of jobs
$32.89 - $35.72
1% of jobs
$35.72 - $38.54
1% of jobs
$38.54 - $41.37
2% of jobs
$10
$21
$41
How much do vlsi chip design internship jobs pay per hour?
What is a VLSI Chip Design Internship job?
A VLSI Chip Design Internship is a training position where interns work on designing, simulating, and testing integrated circuits (ICs) using hardware description languages (HDLs) like Verilog or VHDL. Interns gain hands-on experience with tools for chip design, verification, and physical layout while working alongside experienced engineers. The role often involves learning about digital and analog design, ASIC/FPGA development, and semiconductor fabrication processes. This internship helps students or recent graduates develop skills needed for careers in semiconductor and electronic design industries.
What kind of projects or tasks can I expect to work on during a VLSI Chip Design Internship?
As a VLSI Chip Design Intern, you will typically assist in various stages of the integrated circuit (IC) development process, such as schematic design, simulation, verification, and layout. You may help design logic blocks, validate circuits through simulation, or use EDA tools to optimize performance and power consumption. Interns often work within teams alongside experienced VLSI engineers, gaining exposure to real-world chip design cycles and industry best practices. This hands-on experience helps you build valuable technical skills, understand industry workflows, and prepare for a career in semiconductor design.
What are the key skills and qualifications needed to thrive in the Vlsi Chip Design Internship position, and why are they important?
To excel as a VLSI Chip Design Intern, you need a solid background in electrical engineering concepts, digital and analog circuit design, and familiarity with VLSI fundamentals, typically provided by ongoing or completed coursework in electrical or computer engineering. Experience with electronic design automation (EDA) tools like Cadence, Synopsys, or Mentor Graphics, as well as knowledge of hardware description languages such as Verilog or VHDL, is highly valued. Strong problem-solving abilities, attention to detail, and effective communication skills help you collaborate with engineering teams and adapt to project demands. These competencies are essential for producing high-quality chip designs, meeting project deadlines, and succeeding in a dynamic, innovation-driven environment.

Nvidia rating
9.6
Based on 17 frontline employees who took The Breakroom Quiz
8th of 245 rated software companies
Job description
A key part of NVIDIA's strength is to innovate and deliver the highest performance in the world for AI and accelerated computing. We are constantly looking for ways to improve our GPU architecture and maintain our leadership. NVIDIA is seeking a motivated system architect to define future aspects of our GPU through employing pioneering technologies. Your role will be cross-disciplinary, working with software, ASIC design, verification, physical design, VLSI and platform teams. Our system architects excel at pushing the state of the art while making the best engineering trade-offs.
What you will be doing:
Develop GPU architecture innovations and improvements, optimizing along the axes of scalability/modularity, performance and power efficiency, area, yield, effort, and schedule.
Benchmark GPU configurations (core count, memory and interconnect bandwidth) employing advanced packaging; identify optimal designs for future data center workloads.
Develop and enhance architecture analysis infrastructure, including performance simulators, testbench components and analysis tools, to evaluate configurations under different constraints.
Implement and maintain high-level functional and performance models. Analyze application workloads and performance simulation results to identify areas of architecture improvements.
Document architecture specifications; work with ASIC design, software, and VLSI teams to review and explore trade-offs, define solutions, and track progress.
Collaborate with other functional teams (Design, Floorplan, Packaging and Systems Engineering, etc) to validate packaging choices against performance, cost, and scalability targets.
What we need to see:
Master's/PhD in Computer Engineering, Computer Science or related fields (or equivalent experience)
A minimum of 8 years of relevant work experience in GPU or CPU System Architecture development
Proficiency in data analysis (Python, Excel) to correlate configuration changes with performance metrics.
Deep understanding of accelerated computing and AI data center requirements and tradeoffs, including performance bottlenecks, TCO, Power Delivery Network (PDN), DC Networking, etc
Strong communication and interpersonal skills, as well as the ability to thrive in a dynamic, collaborative, distributed team.
Ways to stand out from the crowd:
Experience with GPU architecture, especially in off-chip IO, memory subsystem, and/or Network-on-Chip (NoC)/Interconnect. Knowledgeable in system level functions such as reset and boot, DFT, and power management
Expertise in analyzing performance scaling and bottlenecks at device and system levels for AI/accelerated computing workloads
Knowledgeable in modern packaging technologies, and their costs and benefits
Consistent track record of efficiently implementing complex architectural features
Outstanding problem-solving skills with a focus on optimizing performance, area, complexity, and power
You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993