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Vector Pipeline Jobs (NOW HIRING)

Marvik

Senior Data Engineer

Colorado Springs, CO · On-site

$104K - $141K/yr

Build embeddings and vector pipelines, and the feature/retrieval-ready datasets that RAG, semantic search, and agentic workloads depend on * Make production data AI-ready in practice: well-structured ...

Vector Space Systems

Head of Customer Success

Vector is hiring a Head of Customer Success to build and lead the function that helps customers turn contact-level advertising data into measurable pipeline results. This is a hands-on leadership ...

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Vector Pipeline information

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$96K

$139.2K

$167.5K

How much do vector pipeline jobs pay per year?

As of Aug 7, 2026, the average yearly pay for vector pipeline in the United States is $139,222.00, according to ZipRecruiter salary data. Most workers in this role earn between $129,000.00 and $167,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the vector pipeline position?

To excel in a Vector Pipeline role, candidates typically need a strong background in computer graphics, 3D pipeline development, and programming languages such as Python or C++. Familiarity with industry-standard tools like Autodesk Maya, Houdini, and version control systems is frequently required, along with knowledge of data formats and real-time rendering engines. Strong problem-solving skills, communication, and the ability to collaborate with multidisciplinary teams are invaluable soft skills. These capabilities enable efficient development and maintenance of art asset pipelines, ensuring smooth workflows for artists and technical teams in industries such as animation, gaming, or visual effects.

What is a vector pipeline?

A Vector Pipeline job typically involves managing the flow of vector data in computing processes, often related to graphics rendering, machine learning, or high-performance computing. This role focuses on optimizing how vectorized data is processed through parallel computing techniques, ensuring efficiency and speed. Professionals in this field work with specialized hardware, software frameworks, and algorithms to enhance computational performance.

What are the main responsibilities of a vector pipeline specialist?

A Vector Pipeline specialist is primarily responsible for developing, managing, and optimizing the processes that move graphical assets through different stages of a production. This includes creating scripts and tools to automate repetitive tasks, ensuring compatibility between software packages, and addressing technical issues that arise in the art pipeline. They frequently collaborate with artists, animators, and developers to streamline workflows and improve efficiency. In larger teams, they may also participate in planning meetings and help train other team members on pipeline tools and best practices. This multifaceted role is central to keeping projects on schedule and facilitating smooth creative collaboration.

More about Vector Pipeline jobs
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Vector Pipeline jobs near you
Infographic showing various Vector Pipeline job openings in the United States as of August 2026, with employment types broken down into 94% Full Time, 3% Part Time, and 3% Contract. Highlights an 82% Physical, 3% Hybrid, and 15% Remote job distribution, with an average salary of $139,222 per year, or $66.9 per hour.

Principal Microarchitect (Santa Clara)

Acceler8 Talent

Santa Clara, CA • On-site

Full-time

This job post has expired today. Applications are no longer accepted.

Job description

Senior/Principal Microarchitect — Compute Engine

About the Role

An early-stage semiconductor company is seeking a Senior or Principal Microarchitect to help design the compute engines for a next-generation high-performance accelerator.

This role spans microarchitecture and RTL development, with ownership from early architectural definition through implementation, verification, first silicon, and post-silicon optimization.

You will work closely with architecture, compiler, kernel, verification, and performance teams to define execution pipelines, data movement, memory structures, and programming-model tradeoffs for demanding compute workloads.

What You’ll Do

  • Define and implement compute-engine microarchitecture.
  • Design execution pipelines, scheduling mechanisms, control logic, and issue structures.
  • Architect datapaths, register files, scratchpads, and local memory hierarchies.
  • Support modern floating-point and reduced-precision numerical formats.
  • Optimize designs across performance, utilization, power, area, and implementation complexity.
  • Balance compute throughput against memory bandwidth, latency, and broader SoC constraints.
  • Analyze representative workloads to guide architectural decisions.
  • Evaluate instruction-set and programming-model tradeoffs.
  • Use performance modeling, benchmarking, and profiling to validate design choices.
  • Lead the initial RTL implementation of major compute-engine blocks.
  • Support ongoing RTL development, design verification, synthesis, and timing closure.
  • Participate in emulation, debug, silicon bring-up, and post-silicon performance tuning.
  • Write detailed microarchitecture specifications and implementation plans.
  • Provide technical leadership across architecture and design teams.

What We’re Looking For

  • Strong experience designing AI compute engines, GPUs, vector processors, matrix engines, DSPs, or other specialized accelerator hardware.
  • Proven experience designing complex hardware units composed of multiple interacting blocks.
  • Deep understanding of:
  • Matrix and vector execution pipelines
  • Floating-point arithmetic
  • Reduced-precision computation
  • Scheduling and control
  • Register files and local memories
  • Strong RTL development experience using Verilog or SystemVerilog.
  • Experience taking complex designs from architecture through implementation and verification.
  • Ability to make tradeoffs across performance, power, area, bandwidth, schedule, and verification risk.
  • Strong collaboration skills across architecture, compiler, kernel, RTL, verification, and physical-design teams.

Preferred Experience

  • AI accelerators, GPUs, NPUs, or custom compute silicon.
  • GEMM, tensor, vector, or matrix-processing hardware.
  • Performance modeling and workload analysis.
  • Compiler or kernel interaction with accelerator hardware.
  • Emulation and pre-silicon validation.
  • Post-silicon bring-up and performance tuning.
  • Advanced process-node experience.
  • Master’s degree, PhD, or equivalent practical experience.

Microarchitecture, Microarchitect, Compute Engine, AI Accelerator, NPU, GPU, Tensor Processor, Matrix Engine, Vector Processor, RTL Design, SystemVerilog, Verilog, Execution Pipeline, Instruction Scheduling, Control Logic, Datapath, Register File, Scratchpad Memory, Local Memory, Memory Hierarchy, Matrix Pipeline, Vector Pipeline, Floating Point, FP16, BF16, FP8, FP4, Mixed Precision, Quantization, GEMM, Tensor Operations, Throughput Optimization, Performance per Watt, PPA, Power Optimization, Area Optimization, Memory Bandwidth, ISA Design, Programming Model, Performance Modeling, Workload Analysis, Hardware-Software Co-Design, Compiler Co-Design, Kernel Optimization, Synthesis, Timing Closure, Emulation, Silicon Bring-Up, Post-Silicon Validation, First Silicon

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