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About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As part of the Design Verification Team at Marvell, you will verify complex semiconductor solutions across networking, compute, storage, and infrastructure domains. These designs enable high-speed, low-latency, and power-efficient data movement for data centers, telecom and enterprise networking, including both standard and customer-specific silicon. You will ensure designs meet stringent functional and performance requirements while contributing to next-generation AI and accelerated computing architectures. This includes supporting re-architecture efforts for AI-driven workloads, validating system-level performance, and helping identify and resolve architectural bottlenecks in scalable, high-bandwidth, and energy-efficient platforms.

What You Can Expect

In this role, you will develop and maintain UVM-based testbench components and verification infrastructure for functional verification. You will own verification plans, define coverage and test strategies, and drive verification closure for complex designs. You will collaborate with design teams, participate in design reviews, and mentor junior engineers while promoting best practices in verification methodology and reuse.

Architect, develop, and maintain scalable UVM-based verification environments for complex IP and SoC designs, including reusable testbench components and infrastructure.

Define and drive verification strategy and planning, including test methodologies, coverage models, and sign-off criteria, while ensuring end-to-end verification closure.

Develop and execute advanced constrained-random and directed verification testbenches, perform coverage analysis, and ensure comprehensive functional verification against design specifications.

Perform deep RTL debugging and root-cause analysis of complex functional and system-level issues, working closely with design and architecture teams to ensure high-quality, testable implementations.

Lead verification efforts by conducting design and verification reviews, mentoring junior engineers, and improving automation and regression infrastructure to enhance efficiency and quality.

Communicate effectively with cross-functional teams and stakeholders to present verification status, highlight risks, and drive technical discussions to resolution.

What We're Looking For

Bachelor's degree in Computer Science, Electrical Engineering, or a related field, with 3-5 years of relevant professional experience. Or

Master's degree and/or PhD in Computer Science, Electrical Engineering, or a related field, with 2-3 years of professional experience required.

Solid experience with hardware verification methodologies, including UVM (Universal Verification Methodology), constrained-random verification, functional coverage analysis, and assertion-based verification (SVA).

Strong foundation in digital logic design, finite state machines (FSMs), combinational and sequential circuit design, and computer architecture principles, with familiarity in industry-standard protocols such as AMBA, PCIe, Ethernet, and memory coherency architectures.

In-depth knowledge of SoC/ASIC design and verification flows, with proficiency in RTL simulation and debugging. Capable of resolving complex technical issues independently, exercising sound judgment, and successfully delivering projects with minimal supervision.

Collaborates closely with cross-functional teams and fosters productive working relationships. Possesses strong communication and documentation skills, with the ability to mentor and guide junior engineers by coaching and directing less experienced team members

Experience in C/C++ development, advanced scripting in Python, Perl, or similar languages for automation and tooling, and extensive hands-on experience in Linux environments and command-line utilities.

Expected Base Pay Range (USD)

128,000 - 189,370, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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