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Synthetic Labs Jobs (NOW HIRING)

Latent Labs

Computational Protein Designer

San Francisco, CA · On-site

$24.25 - $29.50/hr

... synthetic biology. Working closely with our Lead Computational Protein Designer, you will play a ... Before building Latent Labs, our team co-developed DeepMind's Nobel-prize winning AlphaFold ...

Latent Labs

Head of Lab Platform

San Francisco, CA · On-site

$124K - $163K/yr

... synthetic biology. You will lead and evolve our experimental capabilities, connecting high ... Before building Latent Labs, our team co-developed DeepMind's Nobel-prize winning AlphaFold ...

Astera Labs

Principal Digital Design Engineer

San Jose, CA · On-site

$159K/yr

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity ... Have experience with EDA tools for Synthesis, Lint, CDC, and Prime Time. * Have experience taking ...

Astera Labs

OR · On-site

Role Overview The AI infrastructure landscape is evolving at breakneck speed, and Astera Labs is at ... Lead FPGA architecture and development including simulation, synthesis, validation, and common ...

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All JobsSynthetic Labs Jobs

Synthetic Labs information

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$44.5K

$76.9K

$149K

How much do synthetic labs jobs pay per year?

As of Jun 16, 2026, the average yearly pay for synthetic labs in the United States is $76,893.00, according to ZipRecruiter salary data. Most workers in this role earn between $53,500.00 and $85,000.00 per year, depending on experience, location, and employer.

What is the difference between Synthetic Labs vs Synthetic Chemist?

AspectSynthetic LabsSynthetic Chemist
CredentialsTypically requires a degree in chemistry or chemical engineeringRequires a degree in chemistry, often with research experience
Work EnvironmentLaboratory settings, manufacturing facilitiesResearch labs, industrial labs, pharmaceutical companies
Industry UsageUsed in manufacturing, product development, and testingFocuses on designing and synthesizing chemical compounds

While Synthetic Labs refer to the facilities or departments involved in chemical synthesis, Synthetic Chemists are the professionals who perform the actual chemical synthesis work. Both are integral to chemical production and research, but the labs are the environment, and the chemists are the specialists conducting the experiments.

What cities are hiring for Synthetic Labs jobs? Cities with the most Synthetic Labs job openings:
What states have the most Synthetic Labs jobs? States with the most job openings for Synthetic Labs jobs include:
Synthetic Labs jobs near you
Physical Design Engineer (Place & Route)

Physical Design Engineer (Place & Route)

Astera Labs

San Jose, CA • On-site

$165K/yr

Other

Posted 9 days ago

Job description

As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person.

Basic Qualifications:

  • Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred.
  • 3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
  • Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

  • Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
  • Block level ownership from architecture to GDSII, driving multiple complex designs to production.
  • Experience with Cadence and/or Synopsys physical design tools/flows.
  • Familiarity and working knowledge of SystemVerilog/Verilog.
  • Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
  • Experience in working with IP vendors for both RTL and hard-macro blocks.
  • Good scripting skills in Tcl, Python, or Perl.

Nice to Have Experience Includes:

  • Knowledge of design for test (DFT).
  • Familiarity with ECO methodologies and tools.
  • Knowledge of LVS/DRC closures.
  • Experience with high-speed SERDES or Ethernet PHY design integration.
  • Experience with clock tree synthesis optimization.
  • Familiarity with PCIe, CXL, or Ethernet connectivity protocols.

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is 135,000 USD - $165,000 USD for Senior Level, and 160,000 USD - 195,000 USD for Staff Level. You will also be eligible for equity and benefits.

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