Own the synthesis-to-signoff flow including synthesis with timing and placement constraints (Genus), STA and power analysis (Tempus), and logical equivalence checking (Conformal) * Lead architecture ...
Own the synthesis-to-signoff flow including synthesis with timing and placement constraints (Genus), STA and power analysis (Tempus), and logical equivalence checking (Conformal) * Lead architecture ...
Principal Engineer, Digital Design Engineer (AI/ML)
Chandler, AZ · On-site
$198K/yr
Own the synthesis-to-signoff flow including synthesis with timing and placement constraints (Genus), STA and power analysis (Tempus), and logical equivalence checking (Conformal) * Lead architecture ...
Principal Engineer, Digital Design Engineer (AI/ML)
Chandler, AZ · On-site
$198K/yr
Own the synthesis-to-signoff flow including synthesis with timing and placement constraints (Genus), STA and power analysis (Tempus), and logical equivalence checking (Conformal) * Lead architecture ...
Electrical Engineer - FPGA Design (DOD cleared)
Tucson, AZ · On-site
Medical
Dental
Vision
PTO
Perform partitioning, coding, simulation, synthesis, place-and-route, and timing closure * Verify designs using directed and constrained-random testing with functional and code coverage * Create ...
Electrical Engineer - FPGA Design (DOD cleared)
Tucson, AZ · On-site
Medical
Dental
Vision
PTO
Perform partitioning, coding, simulation, synthesis, place-and-route, and timing closure * Verify designs using directed and constrained-random testing with functional and code coverage * Create ...
RTL Design Engineer
Chandler, AZ · On-site
$127K - $203K/yr
Medical
Dental
Vision
Retirement
PTO
Design, synthesis, and verification of Verilog/SystemVerilog RTL. * Analysis, debug, and resolution of Lint and CDC issues in the design. * Design convergence to timing closure utilizing RTL ...
RTL Design Engineer
Chandler, AZ · On-site
$127K - $203K/yr
Medical
Dental
Vision
Retirement
PTO
Design, synthesis, and verification of Verilog/SystemVerilog RTL. * Analysis, debug, and resolution of Lint and CDC issues in the design. * Design convergence to timing closure utilizing RTL ...
RTL Design Engineer
Chandler, AZ · On-site
$127K - $203K/yr
Medical
Dental
Vision
Retirement
PTO
Design, synthesis, and verification of Verilog/SystemVerilog RTL. * Analysis, debug, and resolution of Lint and CDC issues in the design. * Design convergence to timing closure utilizing RTL ...
RTL Design Engineer
Chandler, AZ · On-site
$127K - $203K/yr
Medical
Dental
Vision
Retirement
PTO
Design, synthesis, and verification of Verilog/SystemVerilog RTL. * Analysis, debug, and resolution of Lint and CDC issues in the design. * Design convergence to timing closure utilizing RTL ...
Electrical Engineer - FPGA Design (DOD cleared) with Security Clearance
Tucson, AZ · On-site
Medical
Dental
Vision
PTO
Perform partitioning, coding, simulation, synthesis, place-and-route, and timing closure * Verify designs using directed and constrained-random testing with functional and code coverage * Create ...
Electrical Engineer - FPGA Design (DOD cleared) with Security Clearance
Tucson, AZ · On-site
Medical
Dental
Vision
PTO
Perform partitioning, coding, simulation, synthesis, place-and-route, and timing closure * Verify designs using directed and constrained-random testing with functional and code coverage * Create ...
Strong hands-on expertise in synthesis, UPF specification, timing closure, hierarchical implementation, and low-power digital design flows. * Hands-on experience in industry standard EDA tools:
Strong hands-on expertise in synthesis, UPF specification, timing closure, hierarchical implementation, and low-power digital design flows. * Hands-on experience in industry standard EDA tools:
Perform synthesis with timing and placement constraints (Genus), static timing analysis and power analysis (Tempus), and logical equivalence checking (Conformal) * Participate in architecture and ...
Perform synthesis with timing and placement constraints (Genus), static timing analysis and power analysis (Tempus), and logical equivalence checking (Conformal) * Participate in architecture and ...
Principal Engineer Electrical
Gilbert, AZ · On-site
$98K - $147K/yr
Medical
Life
PTO
FPGA/ASIC synthesis, timing analysis, and place & route * FPGA design for space environments or space applications Basic Qualifications: * Bachelor's degree in a Science, Technology, Engineering, or ...
Principal Engineer Electrical
Gilbert, AZ · On-site
$98K - $147K/yr
Medical
Life
PTO
FPGA/ASIC synthesis, timing analysis, and place & route * FPGA design for space environments or space applications Basic Qualifications: * Bachelor's degree in a Science, Technology, Engineering, or ...
Strong hands-on expertise in synthesis, UPF specification, timing closure, hierarchical implementation, and low-power digital design flows. * Hands-on experience in industry standard EDA tools:
Strong hands-on expertise in synthesis, UPF specification, timing closure, hierarchical implementation, and low-power digital design flows. * Hands-on experience in industry standard EDA tools:
Principal Engineer Electrical
Gilbert, AZ · On-site
$98K - $147K/yr
Medical
Life
PTO
FPGA/ASIC synthesis, timing analysis, and place & route * FPGA design for space environments or space applications Basic Qualifications: * Bachelor's degree in a Science, Technology, Engineering, or ...
Principal Engineer Electrical
Gilbert, AZ · On-site
$98K - $147K/yr
Medical
Life
PTO
FPGA/ASIC synthesis, timing analysis, and place & route * FPGA design for space environments or space applications Basic Qualifications: * Bachelor's degree in a Science, Technology, Engineering, or ...
Perform synthesis with timing and placement constraints (Genus), static timing analysis and power analysis (Tempus), and logical equivalence checking (Conformal) * Participate in architecture and ...
Perform synthesis with timing and placement constraints (Genus), static timing analysis and power analysis (Tempus), and logical equivalence checking (Conformal) * Participate in architecture and ...
Senior Clinical Content Consultant - Pharmacist (autoimmune and inflammatory diseases)
Phoenix, AZ · On-site
$117K - $140K/yr
Medical
Dental
Vision
Retirement
PTO
You will couple clinical experience with synthesis of evidence to determine appropriate, meaningful inclusion of new information in referential or data-driven clinical decision support databases. You ...
Senior Clinical Content Consultant - Pharmacist (autoimmune and inflammatory diseases)
Phoenix, AZ · On-site
$117K - $140K/yr
Medical
Dental
Vision
Retirement
PTO
You will couple clinical experience with synthesis of evidence to determine appropriate, meaningful inclusion of new information in referential or data-driven clinical decision support databases. You ...
Senior Engineer I - Physical Design
Chandler, AZ · On-site
Medical
Retirement
Clock tree setup/debug and synthesis for optimal QoR. * General physical implementation procedures. * Multi-voltage island-based floorplan design and support. * Flow development and automation ...
Senior Engineer I - Physical Design
Chandler, AZ · On-site
Medical
Retirement
Clock tree setup/debug and synthesis for optimal QoR. * General physical implementation procedures. * Multi-voltage island-based floorplan design and support. * Flow development and automation ...
Senior Engineer I - Physical Design
Chandler, AZ · On-site
Medical
Retirement
Clock tree setup/debug and synthesis for optimal QoR. * General physical implementation procedures. * Multi-voltage island-based floorplan design and support. * Flow development and automation ...
Senior Engineer I - Physical Design
Chandler, AZ · On-site
Medical
Retirement
Clock tree setup/debug and synthesis for optimal QoR. * General physical implementation procedures. * Multi-voltage island-based floorplan design and support. * Flow development and automation ...
Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)
Scottsdale, AZ · On-site
$122K - $136K/yr
Experience with synthesis tools (Precision, Synplify) * Experience with verification tools (QuestaSim/UVM) * Experience with clock-domain-crossing tools (Questa CDC) * Experience with lab bring-up ...
Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)
Scottsdale, AZ · On-site
$122K - $136K/yr
Experience with synthesis tools (Precision, Synplify) * Experience with verification tools (QuestaSim/UVM) * Experience with clock-domain-crossing tools (Questa CDC) * Experience with lab bring-up ...
Experience with synthesis tools (Precision, Synplify) * Experience with verification tools (QuestaSim/UVM) * Experience with clock-domain-crossing tools (Questa CDC) * Experience with lab bring-up ...
Experience with synthesis tools (Precision, Synplify) * Experience with verification tools (QuestaSim/UVM) * Experience with clock-domain-crossing tools (Questa CDC) * Experience with lab bring-up ...
Must have basic digital RTL coding experience besides synthesis exposure. * Must have experience with at least 8 tapeouts with hands on experience with DFT/Scan. * Ideal candidate will have solid ...
New
Must have basic digital RTL coding experience besides synthesis exposure. * Must have experience with at least 8 tapeouts with hands on experience with DFT/Scan. * Ideal candidate will have solid ...
New
FPGA Design Engineer
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware verification, and implementation. * Collaborate with cross-functional engineering teams to integrate FPGA ...
FPGA Design Engineer
$116K - $160K/yr
Develop RTL and support simulation, synthesis, place and route, timing closure, hardware verification, and implementation. * Collaborate with cross-functional engineering teams to integrate FPGA ...
Principal FPGA/ASIC Engineer - Level 3
Gilbert, AZ · On-site
$79K - $118K/yr
Medical
Dental
Vision
Life
Retirement
PTO
FPGA/ASIC synthesis, timing analysis, and place & route * FPGA design for space environments or space applications Basic Qualifications: * Bachelor's degree in a STEM (Science, Technology ...
Principal FPGA/ASIC Engineer - Level 3
Gilbert, AZ · On-site
$79K - $118K/yr
Medical
Dental
Vision
Life
Retirement
PTO
FPGA/ASIC synthesis, timing analysis, and place & route * FPGA design for space environments or space applications Basic Qualifications: * Bachelor's degree in a STEM (Science, Technology ...
Synthesis information
See Arizona salary details
$88.5K - $92.5K
0% of jobs
$92.5K - $96.4K
0% of jobs
$96.4K - $100.3K
0% of jobs
$100.3K - $104.3K
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$104.3K - $108.2K
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$108.2K - $112.2K
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$112.2K - $116.1K
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$116.1K - $120K
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$120K - $124K
1% of jobs
$126.2K is the 25th percentile. Wages below this are outliers.
$124K - $127.9K
43% of jobs
The median wage is $128.3K / yr.
$127.9K - $131.9K
56% of jobs
$88.5K
$131.9K
How much do synthesis jobs pay per year?
What is the difference between Synthesis vs Chemist?
| Aspect | Synthesis | Chemist |
|---|---|---|
| Required Credentials | Typically a degree in chemistry or related field; specialized training in synthesis techniques | Degree in chemistry; broader focus including analysis, testing, and research |
| Work Environment | Laboratories, manufacturing plants, R&D facilities | Laboratories, research institutions, industry settings |
| Employer & Industry Usage | Pharmaceutical, chemical manufacturing, biotech | Pharmaceutical, chemical, academic, industrial research |
| Common Search & Comparison | Yes | Yes |
While both Synthesis and Chemist roles involve working in chemistry-related environments, Synthesis specialists focus primarily on creating chemical compounds through specific processes. Chemists have a broader scope, including analysis, testing, and research. Understanding these differences helps clarify career paths and job expectations in the chemical industry.
What is a synthesis job?
How does a synthesis professional typically collaborate with cross-functional teams during a project?
What are the key skills and qualifications needed to thrive as a synthesis chemist?
What are popular job titles related to Synthesis jobs in Arizona?
For Synthesis jobs in Arizona, the most frequently searched job titles are:
What job categories do people searching Synthesis jobs in Arizona look for?
The top searched job categories for Synthesis jobs in Arizona are:

Full-time
Re-posted 2 days ago
Analog Devices rating
8.5
Based on 17 frontline employees who took The Breakroom Quiz
33rd of 157 rated electronics manufacturers
Job description
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.
As a Principal Digital Design Engineer, you will lead the architecture and implementation of complex digital subsystems within ADI's mixed-signal and power management ICs. You will drive the adoption of AI/ML techniques to transform design automation, optimization, and productivity across the digital design flow. Your work will span multiple business units and directly shape how ADI integrates advanced digital functionality into next-generation products.
Key Responsibilities
- Drive adoption of AI/ML methodologies to optimize synthesis, timing closure, power estimation, and design space exploration
- Define and lead digital architecture for complex SoCs and mixed-signal ICs, including control logic, digital interfaces, and on-chip processing
- Lead RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power targets
- Own the synthesis-to-signoff flow including synthesis with timing and placement constraints (Genus), STA and power analysis (Tempus), and logical equivalence checking (Conformal)
- Lead architecture and design reviews, assessing trade-offs across timing, area, power, and testability
- Influence design flows, IP reuse strategies, and product roadmaps across multiple projects
- Collaborate with analog design teams to define and integrate digital-analog interfaces and control architectures
- MSEE or MSCE with 10+ years of digital IC design experience, or PhD with 8+ years (BSEE/BSCE with equivalent depth considered)
- Expert-level RTL design in Verilog/SystemVerilog with proven track record of complex digital subsystem delivery
- Track record of leading digital designs from architecture through tape-out, silicon validation, and production release
- Strong scripting skills (Python, Tcl, shell) with experience applying AI/ML techniques to enhance productivity
- Deep knowledge of synthesis, static timing analysis, DFT (scan, ATPG, BIST), and clock domain crossing methodologies
- Proficiency with Cadence digital design tools: Genus, Innovus, Tempus, Conformal
- Excellent presentation, technical writing, and communication skills
- Working knowledge of place-and-route (Innovus), floorplanning, and physical-aware design techniques
- Experience with low-power design techniques including multi-voltage domains, power gating, and UPF
- Familiarity with digital interfaces (I2C, SPI, UART) and mixed-signal SoC integration
- Strong analytical and problem-solving abilities
- Ability to work effectively in a collaborative team environment
- Development and deployment of AI/ML-driven workflows that measurably improve design quality, turnaround time, or coverage
- Full digital subsystem architecture ownership from specification through silicon bring-up and production validation
- Clock domain crossing analysis, lint, and formal verification for multi-clock digital architectures
- DFT strategy and implementation including scan insertion, ATPG pattern generation, and fault coverage closure
- Partner with analog design, verification, and applications teams to define digital control architectures that meet system-level requirements
- Champion AI/ML-driven improvements to digital design workflows, sharing results and best practices across teams
- Contribute to organizational knowledge through design reviews and cross-team technical forums
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: Experienced
Required Travel: No
Shift Type: 1st Shift/Days
What Analog Devices employees say
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Hours and flexibility
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Get the full story on Breakroom
About Analog Devices
Sourced by ZipRecruiter
Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect.
Industry
Electrical equipment, appliance, and component manufacturing
Company size
5,001 - 10,000 Employees
Headquarters location
Norwood, MA, US
Year founded
1965