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Substrate Manager Jobs in California (NOW HIRING)

Attalon, Inc.

Coating Production Manager

Murrieta, CA · On-site

$100K - $138K/yr

The manager oversees production personnel, enforces standards, drives structured training, and ... Audit setups, chamber prep, substrate cleaning, traveler documentation, and process execution for ...

Attalon, Inc.

Coating Production Manager

Murrieta, CA · On-site

$100K - $138K/yr

The manager oversees production personnel, enforces standards, drives structured training, and ... Audit setups, chamber prep, substrate cleaning, traveler documentation, and process execution for ...

Cspeed

Package Design & Layout Engineer

Palo Alto, CA · On-site

DRC, connectivity/LVS-style netlist checks, and cross-domain consistency between die, package, substrate, and board. * Manage netlists for heterogeneous assemblies across revisions and product ...

Google

Package Design Engineer

Sunnyvale, CA · On-site

$159K/yr

Develop and implement the methodology and CAD flow for efficient substrate design and enhanced productivity. * Manage and drive co-design initiatives across chip, package, and system levels ...

Cspeed

Package Design & Layout Engineer

Palo Alto, CA · On-site

DRC, connectivity/LVS-style netlist checks, and cross-domain consistency between die, package, substrate, and board. * Manage netlists for heterogeneous assemblies across revisions and product ...

Entrada Ventures

Package Engineer

Palo Alto, CA · On-site

$180K - $240K/yr

Manage subcontractors and work directly with TSMC and/or OSAT on bumping, substrate options, and advanced packaging flows. * Partner with IC design, physical design, SI/PI, and board teams to ensure ...

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Substrate Manager information

What is a substrate manager?

Substrate Managers are professionals responsible for overseeing the management, sourcing, and quality control of substrates—materials or surfaces on which processes such as printing, electronics fabrication, or biological cultures are performed. They coordinate with suppliers, manage inventory, and ensure that substrates meet the required specifications for production. Substrate Managers play a key role in industries like semiconductor manufacturing, printing, and biotechnology, ensuring that the correct materials are available for efficient and high-quality production.

What are some typical challenges a substrate manager may face when coordinating between suppliers and production teams?

A Substrate Manager often encounters challenges related to ensuring the timely delivery and consistent quality of raw materials from suppliers. Balancing supplier schedules with the production team's needs can be complex, especially if there are unexpected delays or specification changes. Effective communication, proactive problem-solving, and building strong relationships with both suppliers and internal teams are crucial for overcoming these obstacles and maintaining smooth production operations.

What are the key skills and qualifications needed to thrive as a substrate manager, and why are they important?

To thrive as a Substrate Manager, you need expertise in materials science, process engineering, and quality control, often supported by a degree in engineering or a related technical field. Familiarity with substrate manufacturing equipment, ERP systems, and certifications such as Six Sigma or ISO standards is typically required. Strong project management, leadership, and problem-solving abilities are vital soft skills for coordinating teams and driving process improvements. These competencies are crucial for ensuring efficient production, maintaining high-quality standards, and meeting operational goals in substrate manufacturing environments.

What is the difference between Substrate Manager vs Equipment Manager?

AspectSubstrate ManagerEquipment Manager
CredentialsTypically requires a degree in materials science, engineering, or related fieldUsually requires engineering or technical certifications, with a focus on machinery and equipment
Work EnvironmentWorks in semiconductor, electronics, or manufacturing facilities managing substrate materialsWorks in manufacturing plants overseeing machinery and equipment maintenance
Industry UsageCommonly used in semiconductor, electronics, and advanced manufacturing industriesUsed across various manufacturing sectors including electronics, automotive, and industrial production

The Substrate Manager focuses on managing substrate materials used in manufacturing processes, ensuring quality and supply chain efficiency. In contrast, the Equipment Manager oversees machinery and equipment maintenance to ensure operational uptime. Both roles require technical knowledge but differ in their focus areas within manufacturing environments.

What cities in California are hiring for Substrate Manager jobs?

Cities in California with the most Substrate Manager job openings:

Infographic showing various Substrate Manager job openings in California as of August 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution.

Manager, Package Design Engineering

San Jose, CA • On-site

Astera Labs
Semiconductor and Electronic Component Manufacturing • 11 - 50 employees
Learn more about Astera Labsexternal

Full-time

Re-posted 20 days ago

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you'll own the end-to-end delivery of advanced IC packaging solutions-from early architecture definition through production ramp-enabling the next generation of AI infrastructure and connectivity products.
As the semiconductor industry races toward chiplet-based architectures, 2.5D/3D integration, and ever-increasing bandwidth demands, packaging has become a critical differentiator. You'll build and mentor a high-performing team while driving cross-functional execution with silicon architecture, SIPI, PCB, validation, manufacturing, and external partners including substrate vendors and OSATs. Your work will directly impact Astera Labs' ability to deliver industry-leading PCIe, CXL, and Ethernet connectivity solutions to the world's most demanding hyperscale and AI customers.
This role offers the opportunity to shape design methodology, establish scalable standards, and enable chip-package-board co-design frameworks across multiple product lines in a fast-moving, innovation-driven environment.
Key Responsibilities
  • Team Leadership & Execution
    • Build, mentor, and scale a high-performing package design engineering team with clear ownership, accountability, and execution flows
    • Establish design templates, standards, and best-known methods (BKMs) across multiple concurrent programs
    • Lead design reviews, audits, and issue resolution through bring-up and production ramp
  • Package Design Delivery
    • Own end-to-end package design execution including FCBGA/FCCSP, monolithic, multi-die, and chiplet-based designs from concept feasibility through tape-out and production
    • Define and review substrate stack-ups, pad stacks, routing strategies, and design constraints to meet electrical, thermal, mechanical, and manufacturability requirements
    • Drive technical tradeoffs across performance, cost, yield, and schedule, ensuring high-quality design closure and on-time delivery
  • Cross-Functional Collaboration
    • Partner with SIPI, silicon architecture, system/board design, and product teams to drive chip-package-board co-design and resolve system-level challenges
    • Collaborate with OSATs and substrate vendors to ensure design feasibility, manufacturability, and alignment with evolving design rules and technology roadmaps
    • Support adoption of advanced packaging technologies such as 2.5D, chiplet, CPO/CPC, and heterogeneous integration platforms
  • Methodology & Automation
    • Develop and scale design methodologies and automation flows to improve efficiency, quality, and repeatability across the organization

Basic Qualifications
  • Bachelor's degree in Electrical Engineering, Materials Science, or related field
  • 10+ years of progressive experience in IC package design using tools such as Cadence Allegro APD/SiP
  • 5+ years of leadership experience managing teams or technical organizations in IC packaging environments
  • Strong hands-on expertise in end-to-end package design with proven delivery of HVM-ready FCBGA/FCCSP packages using Cadence APD tool
  • Experience with high-speed SerDes systems (PCIe Gen5/6/7, CXL, Ethernet 100G/200G/400G+) and advanced nodes (7nm, 5nm, 3nm)
  • Deep understanding of substrate technologies, stack-ups, routing constraints, assembly processes, and SI/PI fundamentals
  • Proven experience working with OSATs and substrate vendors through development and production ramp
  • Experience working with OSATs and substrate vendors through development and production ramp
  • Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration

Preferred Qualifications
  • Master's degree in Electrical Engineering or related field
  • Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration
  • Experience implementing automation, scripting (Python, SKILL, Tcl), or workflow optimization
  • Background in early package feasibility, platform evaluation, and technology roadmap development
  • Familiarity with chip floor planning, architecture, and system-level tradeoffs
  • Exposure to SIPI modeling and analysis, thermal, and mechanical performance considerations

The base salary range is $230,000 USD - $265,000 USD. This position can be hired as a Manager Level or Director Level. Your base salary will be determined based on location, experience, and employees' pay in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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