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Sta Static Timing Analysis Engineer Jobs in Dallas, TX

Micron

Staff Digital Design Engineer, HBM

Richardson, TX · On-site

$123K/yr

Support synthesis and static timing analysis by crafting and debugging SDC constraints, and ... Experience with synthesis, STA, investigating CDC/RDC issues, and creating timing constraints.

Micron

Staff SoC DFT Engineer, HBM

Richardson, TX · On-site

$123K - $127K/yr

... synthesis, static timing analysis (STA), and physical design teams. * Proficiency using ... Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or ...

Micron

Staff SoC DFT Engineer, HBM

Richardson, TX · On-site

$146K - $247K/yr

... synthesis, static timing analysis (STA), and physical design teams. * Proficiency using ... Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or ...

Micron

HBM SOC Design Engineer

Richardson, TX · On-site

As an HBM SOC Design Engineer, you will be responsible for the design & development of next ... Experience dealing with clock domain crossings (CDC), static timing analysis, synthesis design ...

Texas Instruments

Digital IC Design Engineer

Dallas, TX · On-site

$123K/yr

Familiarity with synthesis and static timing analysis tools (Synopsys Design Compiler, Cadence ... Engineer your future. We empower our employees to truly own their career and development. Come ...

Purple Hires Inc

DFT Engineer

Plano, TX · Remote

Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs ... timing analysis. * Collaborate with RTL design, verification, physical design, STA, and silicon ...

GARVER LLC

Traffic Analysis Engineer

Dallas, TX · On-site

$85 - $125/hr

Traffic Analysis Engineer Dallas, Texas Garver is seeking a highly‑motivated Traffic Analysis ... Developing traffic signal timing plans * Preparing summary documentation and reports * Coordinating ...

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Sta Static Timing Analysis Engineer information

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How much do sta static timing analysis engineer jobs pay per hour?

As of Aug 22, 2026, the average hourly pay for sta static timing analysis engineer in Dallas, TX is $53.05, according to ZipRecruiter salary data. Most workers in this role earn between $42.79 and $61.59 per hour, depending on experience, location, and employer.

What is a STA static timing analysis engineer?

STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.

What are the key skills and qualifications needed to thrive as a STA static timing analysis engineer?

To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.

What are some common challenges faced by STA static timing analysis engineers during project cycles?

STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.

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Sta Static Timing Analysis Engineer jobs near you
Infographic showing various Sta Static Timing Analysis Engineer job openings in Dallas, TX as of July 2026, with employment types broken down into 89% Full Time, 9% Part Time, and 2% Contract. Highlights an 83% Physical, 3% Hybrid, and 14% Remote job distribution, with an average salary of $110,351 per year, or $53.1 per hour.

Senior SOC Physical Design Engineer, HBM

Micron Technology

Richardson, TX • On-site

$123K - $127K/yr

Full-time

Medical, Dental, Vision, PTO

Re-posted 10 days ago

Micron Technology rating

8.6

Company rating: 8.6 out of 10

Based on 43 frontline employees who took The Breakroom Quiz

27th of 159 rated electronics manufacturers

Job description

Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
You will drive physical implementation of advanced high-bandwidth memory (HBM) system-on-chip (SoC) logic and base die designs from netlist through GDSII within the Heterogeneous Integration Group.
You will collaborate closely with design, verification, design for test (DFT), packaging, and manufacturing teams to deliver best-in-class performance, power, and area (PPA) with robust signoff collateral.
This is a hands-on role where you can own blocks or top-level integration across multiple product generations and see your work through tapeout and silicon.
Job Description
Responsibilities will include, but are not limited to:
  • Support physical implementation of SoC blocks from floorplanning through placement, clock tree synthesis (CTS), routing, and optimization to meet performance, power, and area targets.
  • Assist with setup and hold timing closure across multi-mode, multi-corner (MMMC) scenarios using industry tools such as PrimeTime or Tempus under guidance of senior engineers.
  • Collaborate with RTL design and integration teams to ensure correct clocking, reset strategies, and power intent implementation throughout the design.
  • Integrate and implement complex intellectual property (IP) blocks including controllers, interfaces, memory built-in self-test (MBIST), design for test (DFT) logic, buffers, and PHY-adjacent logic with focus on timing and physical correctness.
  • Run and debug physical signoff checks such as design rule checking (DRC), layout versus schematic (LVS), and timing signoff, addressing violations with support from signoff experts.
  • Work with DFT teams to ensure scan and MBIST logic are physically clean and do not negatively impact timing, congestion, or routability.
  • Participate in tapeout readiness activities including engineering change order (ECO) flows, checklists, design reviews, and post-silicon debug by correlating silicon behavior with physical design, static timing analysis, and power analysis.
  • Apply hands-on experience with electronic design automation tools and methodologies while working effectively in a cross-functional, global team environment.
Minimum Qualifications:
  • Hands-on experience with industry electronic design automation tools such as Innovus, Fusion Compiler, IC Validator (ICV), or Calibre for physical design and signoff.
  • Solid understanding of static timing analysis fundamentals, clocking concepts, and Synopsys Design Constraints (SDC).
  • Working knowledge of power intent methodologies including Unified Power Format (UPF) or Common Power Format (CPF), power grid planning, and basic power integrity considerations.
  • Familiarity with physical verification and signoff flows including design rule checking, layout versus schematic, and parasitic awareness.
  • Experience with hierarchical physical design and system-on-chip integration methodologies.
Preferred Qualifications:
  • Experience with HBM or dynamic random-access memory (DRAM) adjacent SoC designs or memory-subsystem-heavy SoCs.
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
  • Minimum three to five years of experience in a related physical design or SoC implementation role.
  • Experience with signal integrity and reliability analysis including IR drop and electromigration using tools such as Ansys.
  • Experience developing or using Tcl or Python scripts to automate physical design checks, reporting, and flow improvements.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn about your right to work click here.
To learn more about Micron, please visit micron.com/careers
For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron's People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

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