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Soc Implementation Engineer Jobs (NOW HIRING)

As a CPU Clock Implementation Engineer, you will be driving the planning, design, implementation ... SoC designs Knowledge of industry standards and practices in physical design, analysis, and ...

As a CPU Clock Implementation Engineer, you will be driving the planning, design, implementation ... SoC designs Knowledge of industry standards and practices in physical design, analysis, and ...

As a CPU Clock Implementation Engineer, you will be driving the planning, design, implementation ... SoC designs Knowledge of industry standards and practices in physical design, analysis, and ...

As a CPU Clock Implementation Engineer, you will be driving the planning, design, implementation ... SoC designs Knowledge of industry standards and practices in physical design, analysis, and ...

DFT Implementation Engineer

Austin, TX · On-site

$141K - $200K/yr

The Role and Impact As a DFT Design Engineer, you will play a pivotal role in shaping Intel ... SoC and IP solutions. Your work will drive innovation, enhance test coverage, and optimize the ...

DFT Implementation Engineer

Austin, TX · On-site

$141K - $200K/yr

The Role and Impact As a DFT Design Engineer, you will play a pivotal role in shaping Intel ... SoC and IP solutions. Your work will drive innovation, enhance test coverage, and optimize the ...

Collaborate with methodology and implementation teams to support corner-case analysis, refine ... Coordinate with SoC-level integration teams to ensure successful block delivery, maintain alignment ...

Coordinate with SoC-level integration teams to ensure successful block delivery, maintain alignment ... Engineering, or related field. Experience and/or education must include: Experience with top level ...

... Engineering, Computer Science, or a related field, or equivalent practical experience. * 10 years of experience with silicon implementation with a focus on high-performance SoC or ASIC development.

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Soc Implementation Engineer information

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How much do soc implementation engineer jobs pay per hour?

As of Sep 10, 2026, the average hourly pay for soc implementation engineer in the United States is $51.41, according to ZipRecruiter salary data. Most workers in this role earn between $38.46 and $61.06 per hour, depending on experience, location, and employer.

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What states have the most Soc Implementation Engineer jobs?

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Principal Engineer, Physical Design

San Diego, CA • On-site

$144K - $148K/yr

Full-time

Re-posted yesterday


Job description

Overview of Role

As a Physical Design Principal Engineer, you will be responsible for the entire SOC implementation and verification flow from RTL-to-GDS that includes floorplan, place and route, CTS, STA, PV/EMIR/Noise/SigEM cleanup and signoff on lower power SoC. You will be joining a team of engineers dedicated to pushing the envelope for a leading fabless wireless semiconductor platform company specializing in extreme low power wireless radio solutions.

Location

  • San Diego or San Jose, CA

Responsibilities

  • Complete entire physical implementation of the block and chip level
  • Perform synthesis and physical implementation steps - synthesis, floor-planning, power delivery, place&route, timing noise, physical verification, IR/RV.
  • Collaborate with the SOC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs
  • Analyze the quality of the floorplan and Customized Clock tree structure and Place & Route
  • Implement ECOs for timing closure
  • Signal EM/Noise and Power IR/EM analysis and fix
  • DRC/LVS/ERC/ANTENNA analysis and clean up
  • Timing verification and signoff
  • Physical verification and sign off

Minimum Qualifications

  • Master's degree or above in electrical/computer science engineering with 10+ years of industry experience, or bachelor's degree in electrical/computer science engineering plus 15+ years of industry experience
  • Strong experience in Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification.
  • The entire SOC implementation and verification flow from RTL-to-GDS that includes fullchip floorplan, place and route, CTS, and layout verification signoff on lower power SoC
  • Netlist (or RTL)-GDS physical implementation experience
  • In depth knowledge of major EDA tools/design flows
  • Strong Cadence experience/background
  • Experience with TSMC N22 or below technology
  • Experience in chip integration and signoff
  • Experience in Perl/TCL language programming

Preferred Qualifications

  • Strong experience in Low-power implementation methodology
  • Strong experience in Advanced timing signoff methodology
  • Knowledge of DFT (BSCAN, MBIST, SCAN) and understanding of their impact on physical design flows
  • Able to independently complete Netlist-GDS P&R, signoff task
  • Proven record in multi-million gate design production tapeouts