ZipRecruiter

Log In

1

Senior Rfic Design Engineer Jobs in Tustin, CA (NOW HIRING)

SpaceX

Sr. ASIC Design Engineer (Starshield)

Irvine, CA · On-site

$160K - $225K/yr

Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers ... Pay range: Sr. ASIC Design Engineer: $160,000.00 - $225,000.00/per year Your actual level and base ...

Vast

Senior Mechanical Design Engineer

Long Beach, CA

$137K - $195K/yr

Vast is looking for a Senior Mechanical Design Engineer , reporting to the Senior Manager of Structures Design, to support the development of the systems that will be required for the design and ...

TAE

Sr. Design Engineer

Irvine, CA · On-site

$125K - $150K/yr

About The Role The Senior Design Engineer will lead the design and development of mechanical systems supporting TAE's R&D and commercial ventures. Projects will range from simple machined components ...

Vast

Senior Electrical Design Engineer

Long Beach, CA

$137K - $195K/yr

Vast is looking for a Senior Electrical Design Engineer, Avionics, reporting to the Director, Avionics, to support the development of the systems that will be required for the design and build of ...

next page

Showing results 1-20

All JobsSenior Rfic Design Engineer JobsSenior Rfic Design Engineer Jobs in Tustin, CA

Senior Rfic Design Engineer information

See Tustin, CA salary details

$73.9K

$141K

$204.4K

How much do senior rfic design engineer jobs pay per year?

As of Jul 2, 2026, the average yearly pay for senior rfic design engineer in Tustin, CA is $141,036.00, according to ZipRecruiter salary data. Most workers in this role earn between $112,700.00 and $165,100.00 per year, depending on experience, location, and employer.

What is a Senior RFIC Design Engineer?

A Senior RFIC (Radio Frequency Integrated Circuit) Design Engineer is an experienced professional who designs, develops, and tests high-frequency integrated circuits used in wireless communication devices. They work extensively with analog and mixed-signal circuits, and are responsible for ensuring the performance, reliability, and manufacturability of RFICs for applications such as mobile phones, Wi-Fi, and IoT devices. In addition to technical design tasks, Senior RFIC Design Engineers often mentor junior engineers, collaborate with cross-functional teams, and contribute to the overall architecture of wireless systems.

What are the key skills and qualifications needed to thrive as a Senior RFIC Design Engineer, and why are they important?

To thrive as a Senior RFIC Design Engineer, you need deep expertise in RF circuit theory, semiconductor physics, and hands-on experience with analog/mixed-signal IC design, usually backed by a master's or PhD in electrical engineering. Mastery of industry-standard EDA tools (such as Cadence Virtuoso, Spectre, and EM simulators) and familiarity with relevant process design kits (PDKs) and lab measurement equipment is essential. Strong analytical thinking, teamwork, and effective communication set outstanding engineers apart. These skills ensure the development of high-performance, reliable RFICs through efficient problem-solving, collaboration, and precise execution in a fast-evolving field.

What is the difference between Senior Rfic Design Engineer vs RFIC Design Engineer?

AspectSenior Rfic Design EngineerRFIC Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering, specialized in RFIC designBachelor's or Master's in Electrical Engineering, with RF focus
Work EnvironmentDesign teams, R&D labs, semiconductor companiesDesign teams, semiconductor firms, integrated circuit companies
Industry UsageUsed in advanced wireless, telecom, and satellite systemsUsed in wireless communication, mobile devices, and RF components

The main difference is that a Senior Rfic Design Engineer typically has more experience and leadership responsibilities in RFIC design projects, whereas an RFIC Design Engineer may be earlier in their career or at a non-senior level. Both roles focus on RF integrated circuit design but differ in seniority and scope of responsibilities.

What are some common challenges faced by Senior RFIC Design Engineers during the chip design and validation process?

Senior RFIC Design Engineers often encounter challenges such as meeting stringent performance specifications within tight power and area constraints, managing electromagnetic interference, and ensuring the design complies with fabrication process limitations. Additionally, integrating RF circuits with digital and analog components on the same chip can introduce complex noise coupling issues that must be mitigated through careful layout and simulation. Close collaboration with layout engineers, validation teams, and system architects is essential to address these challenges and to deliver robust, manufacturable designs on schedule.
What job categories do people searching Senior Rfic Design Engineer jobs in Tustin, CA look for? The top searched job categories for Senior Rfic Design Engineer jobs in Tustin, CA are:
What cities near Tustin, CA are hiring for Senior Rfic Design Engineer jobs? Cities near Tustin, CA with the most Senior Rfic Design Engineer job openings:
Senior Rfic Design Engineer jobs near you
Infographic showing various Senior Rfic Design Engineer job openings in Tustin, CA as of June 2026, with employment types broken down into 44% Full Time, 47% Part Time, 3% Temporary, and 6% Contract. Highlights an 96% Physical, 3% Hybrid, and 1% Remote job distribution, with an average salary of $141,036 per year, or $67.8 per hour.
Sr. ASIC Design Engineer (Starshield)

Sr. ASIC Design Engineer (Starshield)

SpaceX

Irvine, CA • On-site

$160K - $225K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 29 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 144 frontline employees who took The Breakroom Quiz

14th of 60 rated aerospace companies

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. ASIC DESIGN ENGINEER (STARSHIELD)
Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.
RESPONSIBILITIES:
  • Design digital ASICs and/or FPGAs for Starshield projects.
  • Evaluate architectural trade-offs based on features, performance requirements and system limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
  • Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
  • Work closely with verification team to ensure all aspects of the design are covered and verified.
  • Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
  • Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab measurements.

BASIC QUALIFICATIONS:
  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 5+ years of experience in RTL implementation and/or FPGA/ASIC development.

PREFERRED SKILLS AND EXPERIENCE:
  • Experience solving problems including clock domain crossings and power optimization.
  • Experience developing complex ASICs.
  • Experience with multicore CPU subsystem design.
  • Experience with standard bus protocols (e.g. AXI, AHB, etc.).
  • Experience with embedded processors.
  • Experience with high speed and low power design techniques.
  • Scripting skills (Python, TCL etc.).
  • Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
  • Ability to work in a dynamic environment with changing needs and requirements.
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis.
  • Enjoy being challenged and learning new skills.

ADDITIONAL REQUIREMENTS:
  • Ability to work long hours and weekends as necessary to support critical milestones.
  • Willingness to travel for off-site testing.
  • An active TS-SCI clearance may provide the opportunity for you to work on sensitive SpaceX missions; if so, you will be subject to pre-employment drug and random drug and alcohol testing.

COMPENSATION AND BENEFITS:
Pay range:
Sr. ASIC Design Engineer: $160,000.00 - $225,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Those with an active clearance will receive a 10% differential, up to an additional $15,000 annually, once officially briefed into a classified program.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.
ITAR REQUIREMENTS:
  • To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.

What SpaceX employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

Apply