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Senior Rfic Design Engineer Jobs in Seattle, WA (NOW HIRING)

SpaceX

EDA Engineer (RFIC Engineering)

Redmond, WA · On-site

We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... senior guidance BASIC QUALIFICATIONS: * Bachelor's degree in electrical engineering, computer ...

Summation

Senior Design Engineer

Bellevue, WA · On-site

$100 - $130/hr

As a Senior Design Engineer, you will ship beautiful, high-performance product experiences in production code, lead our design system, prototype new interactions, and raise the bar on accessibility ...

SpaceX

RFIC Layout Designer (RFIC Engineering)

Redmond, WA · On-site

$120K - $175K/yr

We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... engineer to determine pad locations * Accurately estimate the schedule for the layout work and ...

Actalent

Senior Mechanical Design Engineer

Bothell, WA

$102K - $140K/yr

Senior Mechanical Design Engineer The Senior Mechanical Design Engineer plays a key role in the design, procurement, fabrication, assembly, integration, start-up, and commissioning of very large ...

System One

Senior Mechanical Design Engineer

Bellevue, WA · Remote

$92K - $126K/yr

Senior Mechanical Design Engineer (Core Components) Location: Bellevue, WA Job Type: Contract - Remote Schedule: 40 hours/week System One is seeking a highly motivated Senior Mechanical Design ...

Protingent

Senior Mechanical Design Engineer

Bellevue, WA · On-site

$52 - $85/hr

Senior Mechanical Design Engineer Position Description: Protingent Staffing has an exciting contract Senior Mechanical Design Engineer opportunity. Job Responsibilities: * Coordinate and utilize ...

Terex Corporation

Design Engineer II/Sr

Redmond, WA · On-site

$91K - $140K/yr

Design Engineer II/Sr Redmond, WA Onsite At Terex / Genie we believe in fostering a vibrant and inclusive work culture where every person is empowered to thrive. We're dedicated to driving quality ...

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All JobsRfic Design Engineer JobsSenior Rfic Design Engineer JobsSenior Rfic Design Engineer Jobs in Seattle, WA

Senior Rfic Design Engineer information

See Seattle, WA salary details

$80.2K

$153.2K

$221.9K

How much do senior rfic design engineer jobs pay per year?

As of Aug 19, 2026, the average yearly pay for senior rfic design engineer in Seattle, WA is $153,153.00, according to ZipRecruiter salary data. Most workers in this role earn between $122,300.00 and $179,200.00 per year, depending on experience, location, and employer.

What is a Senior RFIC Design Engineer?

A Senior RFIC (Radio Frequency Integrated Circuit) Design Engineer is an experienced professional who designs, develops, and tests high-frequency integrated circuits used in wireless communication devices. They work extensively with analog and mixed-signal circuits, and are responsible for ensuring the performance, reliability, and manufacturability of RFICs for applications such as mobile phones, Wi-Fi, and IoT devices. In addition to technical design tasks, Senior RFIC Design Engineers often mentor junior engineers, collaborate with cross-functional teams, and contribute to the overall architecture of wireless systems.

What are some common challenges faced by Senior RFIC Design Engineers during the chip design and validation process?

Senior RFIC Design Engineers often encounter challenges such as meeting stringent performance specifications within tight power and area constraints, managing electromagnetic interference, and ensuring the design complies with fabrication process limitations. Additionally, integrating RF circuits with digital and analog components on the same chip can introduce complex noise coupling issues that must be mitigated through careful layout and simulation. Close collaboration with layout engineers, validation teams, and system architects is essential to address these challenges and to deliver robust, manufacturable designs on schedule.

What are the key skills and qualifications needed to thrive as a Senior RFIC Design Engineer, and why are they important?

To thrive as a Senior RFIC Design Engineer, you need deep expertise in RF circuit theory, semiconductor physics, and hands-on experience with analog/mixed-signal IC design, usually backed by a master's or PhD in electrical engineering. Mastery of industry-standard EDA tools (such as Cadence Virtuoso, Spectre, and EM simulators) and familiarity with relevant process design kits (PDKs) and lab measurement equipment is essential. Strong analytical thinking, teamwork, and effective communication set outstanding engineers apart. These skills ensure the development of high-performance, reliable RFICs through efficient problem-solving, collaboration, and precise execution in a fast-evolving field.

What is the difference between Senior Rfic Design Engineer vs RFIC Design Engineer?

AspectSenior Rfic Design EngineerRFIC Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering, specialized in RFIC designBachelor's or Master's in Electrical Engineering, with RF focus
Work EnvironmentDesign teams, R&D labs, semiconductor companiesDesign teams, semiconductor firms, integrated circuit companies
Industry UsageUsed in advanced wireless, telecom, and satellite systemsUsed in wireless communication, mobile devices, and RF components

The main difference is that a Senior Rfic Design Engineer typically has more experience and leadership responsibilities in RFIC design projects, whereas an RFIC Design Engineer may be earlier in their career or at a non-senior level. Both roles focus on RF integrated circuit design but differ in seniority and scope of responsibilities.

What are the most commonly searched types of Rfic Design Engineer jobs in Seattle, WA?

The most popular types of Rfic Design Engineer jobs in Seattle, WA are:

Senior Rfic Design Engineer jobs near you
Infographic showing various Senior Rfic Design Engineer job openings in Seattle, WA as of June 2026, with employment types broken down into 81% Part Time, 6% Temporary, and 13% Contract. Highlights an 96% Physical, 3% Hybrid, and 1% Remote job distribution, with an average salary of $153,153 per year, or $73.6 per hour.

EDA Engineer (RFIC Engineering)

SpaceX

Redmond, WA • On-site

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 4 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 148 frontline employees who took The Breakroom Quiz

17th of 72 rated aerospace companies

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
EDA ENGINEER (RFIC ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, hands-on, proactive, and intellectually curious EDA Engineer to help support and improve the IC design environment used by silicon design, layout, verification, physical design, and methodology teams. The role focuses on keeping EDA tools reliable, PDK and flow usage reproducible, and designers productive across analog/RF/mixed-signal and digital silicon workflows.
This is a growth-oriented role for an engineer with strong fundamentals in electrical engineering, computer engineering, computer science, Linux, scripting, or IC design tools. The engineer will partner design teams, other EDA engineers, IT/server teams, foundries, and EDA vendors to triage production issues, improve tool flows, build lightweight automation, maintain documentation, and convert repeated support issues into reusable methodology.
RESPONSIBILITIES:
  • Support day-to-day EDA/CAD workflows for RFIC and silicon engineering teams, including tool launch, environment setup, PDK usage, simulation, physical verification, extraction, and related Linux workflows
  • Support analog/RF/mixed-signal specific flows (Virtuoso, Spectre, EM tools, etc.) in addition to digital and physical verification flows
  • Assist with PDK installation, qualification, version tracking, release notes, and deployment support for supported foundry processes
  • Triage DRC, LVS, PEX, simulation, EM, license, HPC, and environment issues using reproducible debug practices: command, log path, tool version, PDK version, run directory, expected result, actual result, and reproduce status
  • Maintain and improve tool launch wrappers, setup scripts, environment modules, path configuration, project templates, and onboarding material
  • Build lightweight automation in Python, Tcl, SKILL, shell, Perl, Makefile, or similar languages for log collection, preflight checks, license/tool health checks, regression reporting, and recurring issue reduction
  • Create and run targeted QA tests for PDK updates, tool upgrades, wrapper changes, vendor patches, and flow changes before broad deployment
  • Maintain clear runbooks and Confluence documentation for common EDA flows, including DRC/LVS/PEX debug, Cadence/Virtuoso setup, simulation setup, HPC job submission, license issues, and common user errors
  • Partner with design, layout, verification, physical design, IT/HPC, foundry, and EDA vendor teams to resolve blocked flows and improve methodology robustness
  • Identify recurring support patterns and help convert one-off fixes into durable flow changes, documentation, automation, or vendor/IT escalations
  • Support configuration-management and data-management workflows, such as Perforce, Cliosoft, or similar systems, as needed for silicon design teams
  • Contribute to modern EDA workflow improvements, including AI-assisted log triage, rule-deck validation, issue classification, signoff reporting, and designer self-service tools under senior guidance

BASIC QUALIFICATIONS:
  • Bachelor's degree in electrical engineering, computer engineering, or computer science
  • 2+ years of experience in EDA/CAD support, IC design flow development, silicon design, physical verification, verification infrastructure, and/or CAD automation

PREFERRED SKILLS AND EXPERIENCE:
  • Master's degree in electrical engineering, computer engineering, computer science, or a related technical field; or equivalent practical experience
  • Hands-on experience using or supporting at least one major EDA flow, such as Cadence Virtuoso/Spectre, Siemens Calibre, Synopsys/Cadence digital tools, Keysight ADS, EMX/HFSS, or similar tools
  • Practical Linux and scripting experience with Python, shell, Tcl, Perl, Makefile, SKILL, or similar languages
  • Ability to independently triage well-scoped user issues, own small flow improvements, document resolutions, and escalate with clear evidence when needed
  • Experience with Cadence Virtuoso, ADE Explorer/Assembler, Spectre, SKILL, design libraries, CDF, techfiles, display resources, or analog/RF/mixed-signal design flows
  • Experience with Siemens Calibre DRC/LVS/PEX/xRC, Synopsys ICV/StarRC, Cadence Pegasus/Quantus, or related physical verification/extraction tools
  • Exposure to PDK installation, PDK QA, foundry design-rule manuals, rule decks, model files, LVS mapping, extraction setup, or PDK release management
  • Exposure to digital design and verification flows such as simulation, regressions, synthesis, STA, power analysis, formal/lint, or regression infrastructure
  • Familiarity with HPC environments, job schedulers such as Slurm or LSF, license servers, FlexNet, Linux modules, wrappers, NFS/storage, and shared compute systems
  • Ability to write clean scripts, parse logs, build sanity checks, and turn repeated errors into automated preflight checks or user-facing runbooks
  • Interest in AI/LLM-assisted EDA workflows, including log triage, runbook retrieval, flow diagnostics, test generation, and signoff report automation

ADDITIONAL REQUIREMENTS:
  • Ability to work long hours and weekends as necessary to support meeting critical milestones

COMPENSATION AND BENEFITS:
Pay Range:
Level 1: $125,000.00 - $150,000.00
Level 2: $145,000.00 - $175,000.00
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees in Washington State accrue paid sick time in compliance with state and federal law. Company shuttles are offered to employees for roundtrip travel from select Seattle locations to the SpaceX Redmond office Monday to Friday.
ITAR REQUIREMENTS:
  • To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.

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About SpaceX

Sourced by ZipRecruiter

Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US

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