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Senior Rfic Design Engineer Jobs in El Segundo, CA

Vast is looking for a Senior Electrical Design Engineer, Avionics, reporting to the Director, Avionics, to support the development of the systems that will be required for the design and build of ...

Senior FPGA Design Engineer

Torrance, CA · On-site

$150K - $200K/yr

Senior FPGA Design Engineer Reporting To: Engineer, Sr. Staff Work Schedule: Hybrid - Torrance, CA Moog is looking for a Sr. FPGA / Digital Design Engineer to develop high speed digital circuit ...

Senior FPGA Design Engineer

Torrance, CA · Hybrid

$150K - $200K/yr

Senior FPGA Design Engineer Reporting To: Engineer, Sr. Staff Work Schedule: Hybrid - Torrance, CA Moog is looking for a Sr. FPGA / Digital Design Engineer to develop high speed digital circuit ...

LinkedIn: Senior Design Engineer - Turbomachinery An advanced aerospace and propulsion engineering company is seeking an experienced Senior Design Engineer to support the development of next ...

Design Engineer III

Burbank, CA · On-site

$111K - $152K/yr

Senior plc is an international, market-leading, engineering solutions provider with 19 operating ... The employee is part of the Design Engineering Team and shall serve as a stress analysis and ...

Design Engineer III

Burbank, CA · On-site

$111K - $153K/yr

Senior plc is an international, market-leading, engineering solutions provider with 19 operating ... The employee is part of the Design Engineering Team and shall serve as a stress analysis and ...

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Showing results 1-20

Senior Rfic Design Engineer information

See El Segundo, CA salary details

$75.1K

$143.3K

$207.7K

How much do senior rfic design engineer jobs pay per year?

As of Jun 11, 2026, the average yearly pay for senior rfic design engineer in El Segundo, CA is $143,345.00, according to ZipRecruiter salary data. Most workers in this role earn between $114,500.00 and $167,800.00 per year, depending on experience, location, and employer.

What is a Senior RFIC Design Engineer?

A Senior RFIC (Radio Frequency Integrated Circuit) Design Engineer is an experienced professional who designs, develops, and tests high-frequency integrated circuits used in wireless communication devices. They work extensively with analog and mixed-signal circuits, and are responsible for ensuring the performance, reliability, and manufacturability of RFICs for applications such as mobile phones, Wi-Fi, and IoT devices. In addition to technical design tasks, Senior RFIC Design Engineers often mentor junior engineers, collaborate with cross-functional teams, and contribute to the overall architecture of wireless systems.

What are the key skills and qualifications needed to thrive as a Senior RFIC Design Engineer, and why are they important?

To thrive as a Senior RFIC Design Engineer, you need deep expertise in RF circuit theory, semiconductor physics, and hands-on experience with analog/mixed-signal IC design, usually backed by a master's or PhD in electrical engineering. Mastery of industry-standard EDA tools (such as Cadence Virtuoso, Spectre, and EM simulators) and familiarity with relevant process design kits (PDKs) and lab measurement equipment is essential. Strong analytical thinking, teamwork, and effective communication set outstanding engineers apart. These skills ensure the development of high-performance, reliable RFICs through efficient problem-solving, collaboration, and precise execution in a fast-evolving field.

What is the difference between Senior Rfic Design Engineer vs RFIC Design Engineer?

AspectSenior Rfic Design EngineerRFIC Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering, specialized in RFIC designBachelor's or Master's in Electrical Engineering, with RF focus
Work EnvironmentDesign teams, R&D labs, semiconductor companiesDesign teams, semiconductor firms, integrated circuit companies
Industry UsageUsed in advanced wireless, telecom, and satellite systemsUsed in wireless communication, mobile devices, and RF components

The main difference is that a Senior Rfic Design Engineer typically has more experience and leadership responsibilities in RFIC design projects, whereas an RFIC Design Engineer may be earlier in their career or at a non-senior level. Both roles focus on RF integrated circuit design but differ in seniority and scope of responsibilities.

What are some common challenges faced by Senior RFIC Design Engineers during the chip design and validation process?

Senior RFIC Design Engineers often encounter challenges such as meeting stringent performance specifications within tight power and area constraints, managing electromagnetic interference, and ensuring the design complies with fabrication process limitations. Additionally, integrating RF circuits with digital and analog components on the same chip can introduce complex noise coupling issues that must be mitigated through careful layout and simulation. Close collaboration with layout engineers, validation teams, and system architects is essential to address these challenges and to deliver robust, manufacturable designs on schedule.
What job categories do people searching Senior Rfic Design Engineer jobs in El Segundo, CA look for? The top searched job categories for Senior Rfic Design Engineer jobs in El Segundo, CA are:
What cities near El Segundo, CA are hiring for Senior Rfic Design Engineer jobs? Cities near El Segundo, CA with the most Senior Rfic Design Engineer job openings:
Infographic showing various Senior Rfic Design Engineer job openings in El Segundo, CA as of June 2026, with employment types broken down into 96% Full Time, 3% Part Time, and 1% Contract. Highlights an 87% Physical, 6% Hybrid, and 7% Remote job distribution, with an average salary of $143,345 per year, or $68.9 per hour.
Principal ASIC Design Engineer (Starshield)

Principal ASIC Design Engineer (Starshield)

SpaceX

Hawthorne, CA • On-site

$200K - $285K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 8 days ago


SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 144 frontline employees who took The Breakroom Quiz

13th of 60 rated aerospace companies


Job description

PRINCIPAL ASIC DESIGN ENGINEER (STARSHIELD)

Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.

RESPONSIBILITIES:

  • Design digital ASICs and/or FPGAs for Starshield projects.
  • Evaluate architectural trade-offs based on features, performance requirements and system limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
  • Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
  • Work closely with verification team to ensure all aspects of the design are covered and verified.
  • Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
  • Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab measurements.

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering, or computer science.
  • 8+ years of experience in RTL implementation and/or FPGA/ASIC development.

PREFERRED SKILLS AND EXPERIENCE:

  • Experience solving problems including clock domain crossings and power optimization.
  • Experience developing complex ASICs.
  • Experience with multicore CPU subsystem design.
  • Experience with standard bus protocols (e.g. AXI, AHB, etc.).
  • Experience with embedded processors.
  • Experience with high speed and low power design techniques.
  • Scripting skills (Python, TCL etc.).
  • Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
  • Ability to work in a dynamic environment with changing needs and requirements.
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis.
  • Enjoy being challenged and learning new skills.

ADDITIONAL REQUIREMENTS:

  • Ability to work long hours and weekends as necessary to support critical milestones.
  • Willingness to travel for off-site testing.
  • An active TS-SCI clearance may provide the opportunity for you to work on sensitive SpaceX missions; if so, you will be subject to pre-employment drug and random drug and alcohol testing.

COMPENSATION AND BENEFITS:    

Pay range:    
Principal ASIC Design Engineer: $200,000.00 - $285,000.00/per year    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience. Those with an active clearance will receive a 10% differential, up to an additional $20,000 annually, once officially briefed into a classified program.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.


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