RTL Design Engineer
Melbourne, FL · On-site
You will be responsible for RTL coding of blocks specified by you or others. You will also ... signal processing conceptsStrong communication and presentation skills
RTL Design Engineer
Melbourne, FL · On-site
You will be responsible for RTL coding of blocks specified by you or others. You will also ... signal processing conceptsStrong communication and presentation skills
RTL Design Engineer
Cary, NC · On-site
You will be responsible for RTL coding of blocks specified by you or others. You will also ... signal processing conceptsStrong communication and presentation skills
RTL Design Engineer
Cary, NC · On-site
You will be responsible for RTL coding of blocks specified by you or others. You will also ... signal processing conceptsStrong communication and presentation skills
RTL Design Engineer
Waltham, MA · On-site
You will be responsible for RTL coding of blocks specified by you or others. You will also ... signal processing conceptsStrong communication and presentation skills
RTL Design Engineer
Waltham, MA · On-site
You will be responsible for RTL coding of blocks specified by you or others. You will also ... signal processing conceptsStrong communication and presentation skills
... signal processing systems for SirenOpt's metrology platform ... Develop designs from concept through architecture definition, RTL development, modeling, simulation ...
... signal processing systems for SirenOpt's metrology platform ... Develop designs from concept through architecture definition, RTL development, modeling, simulation ...
Perl, JSON and Python) Using GenAI tools (e.g., large language models, AI-assisted code generation) to design, validate, and optimize SystemVerilog RTL code Digital signal processing fundamentals ...
Perl, JSON and Python) Using GenAI tools (e.g., large language models, AI-assisted code generation) to design, validate, and optimize SystemVerilog RTL code Digital signal processing fundamentals ...
RTL Design Engineer
Waltham, MA · On-site
You will be responsible for RTL coding of blocks specified by you or others. You will also ... signal processing conceptsStrong communication and presentation skills
RTL Design Engineer
Waltham, MA · On-site
You will be responsible for RTL coding of blocks specified by you or others. You will also ... signal processing conceptsStrong communication and presentation skills
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · On-site
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · On-site
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · On-site
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · On-site
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · Hybrid
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Senior FPGA / RTL Design Engineer - Signal Processing
Los Angeles, CA · Hybrid
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification ...
RTL Design Engineer
$114K - $199K/yr
Perl, JSON and Python) Using GenAI tools (e.g., large language models, AI-assisted code generation) to design, validate, and optimize SystemVerilog RTL code Digital signal processing fundamentals ...
RTL Design Engineer
$114K - $199K/yr
Perl, JSON and Python) Using GenAI tools (e.g., large language models, AI-assisted code generation) to design, validate, and optimize SystemVerilog RTL code Digital signal processing fundamentals ...
RTL Design Engineer
$162K - $286K/yr
Perl, JSON and Python) Using GenAI tools (e.g., large language models, AI-assisted code generation) to design, validate, and optimize SystemVerilog RTL code Digital signal processing fundamentals ...
RTL Design Engineer
$162K - $286K/yr
Perl, JSON and Python) Using GenAI tools (e.g., large language models, AI-assisted code generation) to design, validate, and optimize SystemVerilog RTL code Digital signal processing fundamentals ...
PHY RTL Design Engineer
Irvine, CA · On-site
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Develop signal processing intensive design for wireless communication SoCs, including: Writing ...
PHY RTL Design Engineer
Irvine, CA · On-site
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Develop signal processing intensive design for wireless communication SoCs, including: Writing ...
PHY RTL Design Engineer
Irvine, CA · On-site
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Develop signal processing intensive design for wireless communication SoCs, including: Writing ...
PHY RTL Design Engineer
Irvine, CA · On-site
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Develop signal processing intensive design for wireless communication SoCs, including: Writing ...
PHY RTL Design Engineer
Irvine, CA · On-site
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Develop signal processing intensive design for wireless communication SoCs, including: Writing ...
PHY RTL Design Engineer
Irvine, CA · On-site
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Develop signal processing intensive design for wireless communication SoCs, including: Writing ...
RTL Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
Experience verifying and debugging RTL , preferably in context of CPU, GPU, video, display or signal processing system. Understanding of micro-architecture and logic design fundamentals, e.g. finite ...
RTL Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
Experience verifying and debugging RTL , preferably in context of CPU, GPU, video, display or signal processing system. Understanding of micro-architecture and logic design fundamentals, e.g. finite ...
Verification Engineer, Digital Signal Processing
Sunnyvale, CA · On-site
$159K/yr
Verify RTL implementations against high-level architectural reference models (MATLAB, C , or ... signal processing blocks. Information collected and processed as part of your Google Careers ...
Verification Engineer, Digital Signal Processing
Sunnyvale, CA · On-site
$159K/yr
Verify RTL implementations against high-level architectural reference models (MATLAB, C , or ... signal processing blocks. Information collected and processed as part of your Google Careers ...
Rtl Signal Processing information
See salary details
$53.5K - $66.2K
3% of jobs
$66.2K - $79K
0% of jobs
$79K - $91.7K
3% of jobs
$91.7K - $104.4K
14% of jobs
$107.8K is the 25th percentile. Wages below this are outliers.
$104.4K - $117.1K
18% of jobs
The median wage is $127.9K / yr.
$117.1K - $129.9K
14% of jobs
$129.9K - $142.6K
22% of jobs
$143.2K is the 75th percentile. Wages above this are outliers.
$142.6K - $155.3K
11% of jobs
$155.3K - $168K
6% of jobs
$168K - $180.8K
6% of jobs
$180.8K - $193.5K
2% of jobs
$53.5K
$131.3K
$193.5K
How much do rtl signal processing jobs pay per year?
As of Jun 23, 2026, the average yearly pay for rtl signal processing in the United States is $131,349.00, according to ZipRecruiter salary data. Most workers in this role earn between $108,500.00 and $147,500.00 per year, depending on experience, location, and employer.
Apple rating
8.1
Based on 662 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
At Apple, we work every day to craft products that enrich people's lives. If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. Are you looking to expand your chip design career and challenge yourself in a technical and multi-disciplinary endeavor? If so, this is an exciting position in the world class Apple mixed-signal silicon design team! ..This role will build upon your solid foundation in digital logic circuits while introducing mixed signal and analog circuit design and features. You will work with a variety of flows fundamental to modern silicon engineering: modeling and integrating high-performance mixed-signal and analog IPs into high-speed digital circuits. This is an excellent opportunity to gain valuable experience in software methods and analysis, which are increasingly crucial across the semiconductor industry. ..As a member of our dynamic team, you will have the exceptional opportunity to help create the next generation of products that will delight and inspire millions of Apple customers every day. You will work to specify, design, verify, and support lab bring-up of sophisticated digital and mixed-signal circuits.
In this job you will be responsible for specifying and/or micro-architecting digital blocks in sophisticated mixed-signal circuits. You will be responsible for RTL coding of blocks specified by you or others. You will also participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will contribute to the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
BS and a minimum of 10 years relevant industry experience
Proven knowledge of RTL design, Verilog and SystemVerilogDeep knowledge of front-end tools (Verilog simulators, linters, CDC, RDC, LEQ, UPF)Low power design methodologies and techniques to reduce dynamic and static IC powerECO design flows and methodologiesProven understanding of mixed signal concepts and experience with analog circuit behavioral modelingProven knowledge of synthesis, static timing and DFTProven knowledge of SystemVerilog assertions, checkers, and other design verification techniquesKnowledge of scripting languages (i.e. Perl, JSON and Python)Using GenAI tools (e.g., large language models, AI-assisted code generation) to design, validate, and optimize SystemVerilog RTL codeDigital signal processing fundamentals including signal processing conceptsStrong communication and presentation skills
In this job you will be responsible for specifying and/or micro-architecting digital blocks in sophisticated mixed-signal circuits. You will be responsible for RTL coding of blocks specified by you or others. You will also participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will contribute to the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.
BS and a minimum of 10 years relevant industry experience
Proven knowledge of RTL design, Verilog and SystemVerilogDeep knowledge of front-end tools (Verilog simulators, linters, CDC, RDC, LEQ, UPF)Low power design methodologies and techniques to reduce dynamic and static IC powerECO design flows and methodologiesProven understanding of mixed signal concepts and experience with analog circuit behavioral modelingProven knowledge of synthesis, static timing and DFTProven knowledge of SystemVerilog assertions, checkers, and other design verification techniquesKnowledge of scripting languages (i.e. Perl, JSON and Python)Using GenAI tools (e.g., large language models, AI-assisted code generation) to design, validate, and optimize SystemVerilog RTL codeDigital signal processing fundamentals including signal processing conceptsStrong communication and presentation skills
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976