Robotics Simulation Jobs in New Mexico (NOW HIRING)

Description
Job Title Embedded Software Development Engineer (R&D Engineer 2/3)
Location Los Alamos, NM, US
Organization Name E-3/Automation, Robotics, and Controls Group
Minimum Salary
Maximum Salary
What You Will Do
This position will be filled at either the Embedded Software Development Engineer R&D 2 or 3 level, depending on the skills of the selected candidate. Additional job responsibilities (outlined below) will be assigned if the candidate is hired at the higher level.
The Automation, Robotics, and Control Group (E-3) is seeking an experienced FPGA/Embedded Software Development Engineer ( Research and Development (R&D) Engineer 2/3) to join our Embedded Systems for Weapons Analysis (ESWA) team here at Los Alamos National Laboratory.
ESWA is a multidisciplinary team that specializes in high-speed data acquisition systems. Our team's expertise is systems engineering, embedded systems for data acquisition, and mechanical design of complex miniaturized systems for harsh conditions. The ESWA team provides support, expertise, and solutions to LANL's flight programs for verification, reliability surveillance, and system development. As part of the ESWA team, you will contribute to informing joint-scope objectives for LANL systems, by providing critical data and performance metrics for flight-tested assets.
In E-3, we are committed to innovation by valuing employees with diverse skills and experience. Our group solves complex challenges with multidisciplinary teams who have a unique set of experiences, ideas, and skills. As part of E-3, you will have an opportunity to work across different programs where you can continue to develop and expand your skills and specific interests.
R&D Engineer 2 ($106,400 - $176,000)
At the R&D Engineer 2 level, you will work to identify and apply digital design methodologies at a quality necessary for deployment in harsh flight environments. You will work closely with other engineers and scientists to develop, deploy, and test firmware and software for on-board data processing and analysis.
R&D Engineer 3 ($122,300 - $206,300)
In addition to what was outlined at the lower level, as an R&D Engineer 3 you participate as a technical leader with recognized, advanced skills in digital hardware design. Project leadership will look to you for in-depth evaluation of design variables and technical decision making. You will continue to build on your strong communication skills through leadership opportunities, collaborations, and mentoring early career staff.
What You Need
Minimum Job Requirements:
Technical Knowledge
FPGA Development: Hands-on experience with FPGA design, development, and testing, including familiarity with major platforms like Xilinx, Altera/Intel, or Lattice. Ability to translate system-level requirements to FPGA requirements, perform initial design, modeling, simulation, and implementation. Working experience with FPGA tools like Xilinx Vivado, XSIM, Intel Quartus, ModelSim, or other synthesis and simulation software. Ability to debug, simulate, and validate FPGA implementations using logic analyzers, oscilloscopes, or integrated debugging tools like Xilinx ILA/ChipScope/SignalTap.
Hardware Description Languages (HDL): Solid knowledge and experience in VHDL and/or Verilog for FPGA design and simulation. Experience using HDL to design and simulate digital circuits, creating Technical Knowledge
FPGA Development: Hands-on experience with FPGA design, development, and testing, including familiarity with major platforms like Xilinx, Altera/Intel, or Lattice. Ability to translate system-level requirements to FPGA requirements, perform initial design, modeling, simulation, and implementation. Working experience with FPGA tools like Xilinx Vivado, XSIM,[WC1.1] Intel Quartus, ModelSim, or other synthesis and simulation software. Ability to debug, simulate, and validate FPGA implementations using logic analyzers, oscilloscopes, or integrated debugging tools like Xilinx ILA/ChipScope[WC2.1]/SignalTap.
Hardware Description Languages (HDL): Solid knowledge and experience in VHDL and/or Verilog for FPGA design and simulation. Experience using HDL to design and simulate digital circuits, creating placement and timing constraints, performing synthesis, place and route, and on-board device configuration.
Digital Logic Design: Proficiency in designing combinational and sequential logic, state machines, and data path architectures.
Digital Signal Processing (DSP): Familiarity with common DSP algorithms and techniques. [OT3.1][WC4.1][MD4.2][OT4.3]
Communication Protocols: Proficiency in designing and implementing interfaces for high-speed communication protocols such as SPI, I2C, UART, SpW, etc.
Problem-Solving: Strong analytical skills and attention to detail for troubleshooting and optimizing FPGA designs. Experience debugging & troubleshooting circuits and prototypes.
Collaboration[OT5.1]

• Demonstrated ability to be an effective member of a multidisciplinary team. Experience providing technical direction and/or guidance to junior staff and peers, as needed
• Demonstrated ability to utilize strong organization skills to accomplish technical tasks while working independently. Receives occasional oversight on specific objectives, as well as on complex problems and solutions
• Demonstrated ability to collaborate with cross-functional teams to optimize designs for performance, cost-effectiveness, and manufacturability. May have limited independent interactions with peers, organizations, and/or sponsors external to the Laboratory.
• Demonstrated ability to clearly communicate technical material verbally, in writing, and in presentations.

Additional Job Requirements for R&D Engineer 3
In addition to what was outlined at the lower level, as an R&D Engineer 3 you participate as a technical leader with recognized, advanced skills in digital hardware design. Project leadership will look to you for in-depth evaluation of design variables and technical decision making. You will continue to build on your strong communication skills through leadership opportunities, collaborations, and mentoring early career staff. placement and timing constraints, performing synthesis, place and route, and on-board device configuration.
Digital Logic Design: Proficiency in designing combinational and sequential logic, state machines, and data path architectures.
Digital Signal Processing (DSP): Familiarity with common DSP algorithms and techniques.
Communication Protocols: Proficiency in designing and implementing interfaces for high-speed communication protocols such as SPI, I2C, UART, SpW, etc.
Problem-Solving: Strong analytical skills and attention to detail for troubleshooting and optimizing FPGA designs. Experience debugging & troubleshooting circuits and prototypes.
Collaboration

• Demonstrated ability to be an effective member of a multidisciplinary team. Experience providing technical direction and/or guidance to junior staff and peers, as needed
• Demonstrated ability to utilize strong organization skills to accomplish technical tasks while working independently. Receives occasional oversight on specific objectives, as well as on complex problems and solutions
• Demonstrated ability to collaborate with cross-functional teams to optimize designs for performance, cost-effectiveness, and manufacturability. May have limited independent interactions with peers, organizations, and/or sponsors external to the Laboratory.
• Demonstrated ability to clearly communicate technical material verbally, in writing, and in presentations.

Additional Job Requirements for R&D Engineer 3
In addition to what was outlined at the lower level, as an R&D Engineer 3 you participate as a technical leader with recognized, advanced skills in digital hardware design. Project leadership will look to you for in-depth evaluation of design variables and technical decision making. You will continue to build on your strong communication skills through leadership opportunities, collaborations, and mentoring early career staff.
Education/Experience at lower level: Position requires a Bachelor's Degree in Engineering from an accredited institution and 4 years of related experience; or, an equivalent combination of education and experience directly related to the occupation.
Education/Experience at higher level : Position requires a Master's Degree in Engineering from an accredited institution and 6 years of related experience; or, an equivalent combination of education and experience directly related to the occupation. At this level a Ph.D. may be preferred.
Desired Qualifications:

• Active Q Clearance or equivalent DoD clearance
• Experience with Advanced Microcontroller Bus Architecture (AMBA), Advanced eXtensible Interface (AXI) and Advanced Peripheral Bus (APB)
• Experience with MATLAB System Generator for DSP with HDL Coder.
• Experience with High-Level Synthesis (HLS) tools like Xilinx HLS or Intel HLS for converting C/C++ to FPGA implementations.
• Experience with advanced, high-performance FPGA families/architectures such as Xilinx UltraScale+ or Intel Stratix.
• Experience with implementing soft or hard processor cores in FPGAs (e.g., MicroBlaze, Nios II) and their integration with custom logic. Familiarity with partitioning functions between hardware and software, including experience with system-on-chip (SoC) FPGA solutions.[WC7.1]
• Proficient experience with scripting tools such as Python, Tcl, or Perl to automate FPGA design, synthesis, and testing processes.
• Familiarity with advanced verification techniques using SystemVerilog and Universal Verification Methodology (UVM).
• Experience working with real-time operating systems (RTOS) or low-latency designs in FPGA environments.
• HW/SW Codesign using System-on-Chip (SoCs) devices with embedded ARM or Microblaze processors
• Experience or knowledge of best practices for maintaining signal integrity in mixed analog/digital designs from circuit design to PCB layout
• Experience with FPGA and digital design tools such as Microchip(Microsemi/Actel), AMD(Xilinx), Lattice, Intel(Altera), Siemens(ModelSim), Synopsys(Synplicity), Aldec.

Work Location : The work location for this position is onsite and located in Los Alamos, NM. All work locations are at the discretion of management.
Position commitment:
Regular appointment employees are required to serve a period of continuous service in their current position in order to be eligible to apply for posted jobs throughout the Laboratory. If an employee has not served the time required, they may only apply for Laboratory jobs with the documented approval of their Division Leader. The position commitment for this position is 1 year.
Note to Applicants:
Due to federal restrictions contained in the current National Defense Authorization Act, citizens of the People's Republic of China-including the special administrative regions of Hong Kong and Macau-as well as citizens of the Islamic Republic of Iran, the Democratic People's Republic of Korea (North Korea), and the Russian Federation, who are not Lawful Permanent Residents ("green card" holders) are prohibited from accessing facilities that support the mission, functions, and operations of national security laboratories and nuclear weapons production facilities, which includes Los Alamos National Laboratory.
Where You Will Work
Located in beautiful northern New Mexico, Los Alamos National Laboratory (LANL) is a multidisciplinary research institution engaged in strategic science on behalf of national security. Our generous benefits package includes:
§ PPO or High Deductible medical insurance with the same large nationwide network
§ Dental and vision insurance
§ Free basic life and disability insurance
§ Paid childbirth and parental leave
§ Award-winning 401(k) (6% matching plus 3.5% annually)
§ Learning opportunities and tuition assistance
§ Flexible schedules and time off (PTO and holidays)
§ Onsite gyms and wellness programs
§ Extensive relocation packages (outside a 50 mile radius)
Additional Details
Directive 206.2 - Employment with Triad requires a favorable decision by NNSA indicating employee is suitable under NNSA Supplemental Directive 206.2 . Please note that this requirement applies only to citizens of the United States. Foreign nationals are subject to a similar requirement under DOE Order 142.3A.
Clearance: Q (Position will be cleared to this level). Selected applicants will be subject to a background investigation conducted by or on behalf of the Federal Government, and must meet eligibility requirements* for access to classified matter. This position requires a Q clearance, and obtaining such clearance requires US Citizenship except in extremely rare circumstances. Dependent upon the position, additional authorization to access classified information may be required, which may or may not be available to dual citizens. Receipt of a Q clearance and additional access authorization ultimately is a decision of the Federal Government and not of Triad.
*Eligibility requirements: To obtain a clearance, an individual must be at least 18 years of age; U.S. citizenship is required except in very limited circumstances. See DOE Order 472.2 for additional information.
New-Employment Drug Test: The Laboratory requires successful applicants to complete a new-employment drug test and maintains a substance abuse policy that includes random drug testing. Although New Mexico and other states have legalized the use of marijuana, use and possession of marijuana remain illegal under federal law. A positive drug test for marijuana will result in termination of employment, even if the use was pre-offer.
Equal Opportunity: Los Alamos National Laboratory is an equal opportunity employer. All employment practices are based on qualification and merit, without regard to protected categor