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Risc V Engineer Jobs (NOW HIRING)

Baidu USA

Senior RTL Design Engineer

Sunnyvale, CA

Knowledge of RISC-V architecture is a plus. Proficiency with hardware (RTL) design in Verilog ... Ability to work well with others and a belief that engineering is a team sport. Knowledge of at ...

Baidu USA

Senior RTL Design Engineer

Sunnyvale, CA · On-site

... RISC-V CPU core generators. • Microarchitecture development and specification. Ensure that ... engineering is a team sport. • Knowledge of at least one object-oriented and/or functional ...

Tenstorrent

$100K - $500K/yr

... developers ... You will own CPU architectural verification, shaping how our out-of-order RISC-V CPUs are validated ...

Tenstorrent

$154K - $188K/yr

At Tenstorrent, we build open, state of the art compute for real workloads and real developers. You will own CPU core-level testbench development and verification, shaping how our out-of-order RISC-V ...

SiFive

CPU Design Intern

Santa Clara, CA · On-site

$32.40 - $39/hr

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future ... Pursuing a Master's or PhD in Computer Engineering, Computer Science, Electrical Engineering, or a ...

SiFive

Principal Verification Engineer

Austin, TX

$134K/yr

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future ... Functional programming experience is not required but helpful * Proficient in troubleshooting and ...

SiFive

Principal Verification Engineer

Austin, TX · On-site

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future ... Functional programming experience is not required but helpful * Proficient in troubleshooting and ...

Apex Informatics

Computer Vision Engineer V

Sunnyvale, CA · On-site

$132K - $156K/yr

Top Skill need solid DSP SW Engineer with recent exp in CV Minimum Qualifications: • Bachelor ... Risc-V CPUs, or Tensilica DSP architectures TOP SKILLS 1. Great in Coding / Know C++ very well.

Nvidia

OR

$119K - $157K/yr

Experience working with RISC-V or similar embedded processor architectures. * Engineering Approach: Deep understanding of software development processes, robust debugging methodologies, and a ...

Baidu USA

CPU Digital Design Engineer

Sunnyvale, CA

$159K/yr

M aster Degree in Electrical Engineering, Computer Science or Computer Engineering. * A t least 3 ... F amiliarity with Symmetric Multi-threading (SMT), ARM/MIPS CPUs, or RISC-V. * F amiliarity with ...

SiFive

Principal Verification Engineer

Santa Clara, CA · On-site

$159K/yr

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future ... Functional programming experience is not required but helpful * Proficient in troubleshooting and ...

Baidu USA

CPU Digital Design Engineer

Sunnyvale, CA · On-site

$159K/yr

Master Degree in Electrical Engineering, Computer Science or Computer Engineering. * At least 3 ... Familiarity with Symmetric Multi-threading (SMT), ARM/MIPS CPUs, or RISC-V. * Familiarity with ...

Ventana Micro Systems

Senior Emulation Engineer

Austin, TX · On-site

$103K - $142K/yr

Ventana is building the highest-performance RISC-V CPUs on the planet--designed for data center, AI ... This is your opportunity to work alongside engineers who built iconic processors like the AMD K6 ...

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Risc V Engineer information

What is the difference between Risc V Engineer vs FPGA Engineer?

AspectRisc V EngineerFPGA Engineer
Required CredentialsBachelor's in Electrical Engineering, Computer Engineering, or related; knowledge of RISC-V architectureBachelor's in Electrical Engineering, Computer Engineering, or related; experience with FPGA design tools
Work EnvironmentHardware/software development, embedded systems, chip designHardware design, digital logic, FPGA programming
Industry UsageSemiconductor companies, embedded systems, processor designTelecommunications, aerospace, digital signal processing

While both roles involve hardware and digital design, Risc V Engineers focus on developing and optimizing RISC-V processor cores and architectures, whereas FPGA Engineers specialize in designing digital circuits on FPGA platforms. Both roles require a strong understanding of hardware description languages and embedded systems, but their applications and tools differ.

What is a RISC-V Engineer?

A RISC-V Engineer is a professional who specializes in designing, developing, and optimizing computer processors and systems based on the RISC-V instruction set architecture (ISA). They work on hardware and software aspects such as microarchitecture design, verification, firmware development, and integrating RISC-V cores into various devices. These engineers often collaborate with teams to implement open-source solutions, improve performance, and ensure compatibility with industry standards. Their work is crucial in advancing open hardware and enabling customizable, energy-efficient computing platforms.

What are some common challenges faced by RISC-V Engineers when working on open-source hardware projects?

RISC-V Engineers often encounter challenges related to the rapidly evolving nature of the open-source RISC-V ecosystem, such as integrating new extensions or toolchains and ensuring compatibility across different hardware implementations. Collaboration with global teams can require clear communication and thorough documentation to maintain project coherence. Additionally, engineers may need to thoroughly test and validate designs, as open-source projects may lack some of the mature verification infrastructure found in proprietary environments. Overcoming these challenges can lead to valuable learning experiences and contribute to career growth within the open-source hardware community.

What are the key skills and qualifications needed to thrive as a RISC-V Engineer, and why are they important?

To thrive as a RISC-V Engineer, you need a solid background in computer architecture, digital design, and embedded systems, often supported by a degree in electrical engineering or computer engineering. Familiarity with hardware description languages (such as Verilog or VHDL), RISC-V toolchains, and simulation/debugging platforms is typically required. Strong problem-solving abilities, attention to detail, and effective teamwork are crucial soft skills in this role. These skills ensure efficient hardware development, innovation, and reliable implementation of open-source processor designs.
Infographic showing various Risc V Engineer job openings in the United States as of May 2026, with employment types broken down into 99% Full Time, and 1% Part Time. Highlights an 95% Physical, 2% Hybrid, and 3% Remote job distribution.
Senior RTL Design Engineer - CPU Frontend

Senior RTL Design Engineer - CPU Frontend

SiFive

Santa Clara, CA • On-site

$158K - $194K/yr

Full-time

Medical, Retirement, PTO

Posted yesterday

Job description

About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive's unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive's phenomenal success and to see why we have won the GSA's prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
Responsibilities
  • Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel.
  • Integrate new design content into SiFive's Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
  • Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
  • Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
  • Collaborate with the performance modeling team for performance exploration and optimization to meet performance goals.
  • Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.

Requirements
  • BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience.
  • 3+ years of design experience.
  • Academic or professional experience with CPU RTL design in one or more of the following areas: instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, TLBs.
  • Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
  • Strong software engineering skills/background, including:
    • Object-oriented, aspect-oriented, and particularly functional programming
    • Templated metaprogramming, in any language
    • Compiler infrastructures, particularly for domain-specific languages
    • Data modeling, particularly intermediate representations for optimizing or transforming compiler passes
    • Test-driven development, particularly ability to write adaptive unit tests
  • Attention to detail and a focus on high-quality design.
  • Ability to work well with others and share the belief that engineering is teamwork.

Nice-to-haves
  • Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software.
  • Knowledge of RISC-V architecture.
  • Expertise in CPU processor designs in one or more of the following areas is a plus: instruction fetch; instruction decode; register renaming and instruction scheduling; vector units; load-store unit.
  • Knowledge of verification principles, testbenches, UVM, and coverage.
  • Experience with Git/Github, Jira, Confluence.

Pay & Benefits
Consistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.
For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.
Base Pay Range
$158,760.00-$194,040.00
In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in
United States of America
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.
California residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document.

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