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Remote Rtl Design Jobs in Arlington, TX (NOW HIRING)

Purple Hires Inc

ASIC Engineer - Remote

Plano, TX · Remote

Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues. * Support ATPG pattern generation, ATPG simulations ...

Purple Hires Inc

DFT Engineer

Plano, TX · Remote

Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs. We are seeking a highly ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

Purple Hires Inc

ASIC DFT Engineer

Plano, TX · Remote

Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs. We are seeking a highly ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

Purple Hires Inc

Senior MBIST Engineer

Plano, TX · Remote

Senior MBIST Engineer Remote- Must be working as per PST time zone Rate- 70-75/hr on C2C Position ... Work closely with DFT, RTL, Physical Design, and Product Engineering teams to resolve ...

All JobsRtl Design JobsRemote Rtl Design JobsRemote Rtl Design Jobs in Arlington, TX

Remote Rtl Design information

See Arlington, TX salary details

$72.4K

$125.4K

$164.2K

How much do remote rtl design jobs pay per year?

As of Aug 18, 2026, the average yearly pay for remote rtl design in Arlington, TX is $125,423.00, according to ZipRecruiter salary data. Most workers in this role earn between $122,400.00 and $122,400.00 per year, depending on experience, location, and employer.

What is a remote RTL design job?

Remote RTL (Register Transfer Level) Design jobs involve creating and verifying digital circuit designs using hardware description languages like Verilog or VHDL, while working from a remote location. RTL designers translate system requirements into functional hardware blocks, simulate their operation, and ensure they meet performance and power specifications. These roles are common in semiconductor and electronics companies, enabling professionals to collaborate with global teams without being onsite. Remote RTL designers typically use cloud-based tools and platforms to access design environments and communicate with colleagues. Strong knowledge of digital logic, hardware design languages, and industry-standard EDA tools is essential for these positions.

What are the key skills and qualifications needed to thrive as a remote RTL design engineer?

To thrive as a Remote RTL Design Engineer, you need a solid background in digital logic design, Verilog or VHDL programming, and a relevant engineering degree. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and knowledge of simulation, synthesis, and timing analysis are typically required. Strong problem-solving, attention to detail, and effective remote communication skills are essential for collaborating with distributed teams. These competencies ensure the creation of reliable, high-performance hardware designs and efficient teamwork in a remote environment.

What are some common challenges faced by remote RTL design engineers, and how can they be addressed?

Remote RTL Design engineers often encounter challenges such as effective communication with cross-functional teams, managing version control for hardware description files, and ensuring timely feedback on design iterations. To address these, many teams utilize collaborative tools like version control systems (e.g., Git), regular video meetings, and shared project management platforms. Establishing clear documentation and proactive communication habits can further minimize misunderstandings and keep projects on track, fostering a productive remote work environment.

What is the difference between Remote Rtl Design vs Remote Digital IC Design?

AspectRemote Rtl DesignRemote Digital IC Design
Required CredentialsBachelor's in Electrical Engineering or related; knowledge of HDL (VHDL/Verilog)Bachelor's in Electrical Engineering or related; knowledge of HDL and circuit design
Work EnvironmentDesigning RTL code, simulation, verification, often in a collaborative team settingDesigning digital integrated circuits, layout, verification, often in a team
Industry UsageSemiconductor, electronics companies, chip design firmsSemiconductor, electronics, and integrated circuit manufacturing

Remote Rtl Design focuses on creating and verifying RTL code for digital circuits, while Remote Digital IC Design involves designing entire integrated circuits. Both roles require similar technical skills and often overlap in the semiconductor industry, but they differ in scope and specific tasks.

What are popular job titles related to Remote Rtl Design jobs in Arlington, TX?

For Remote Rtl Design jobs in Arlington, TX, the most frequently searched job titles are:

What job categories do people searching Remote Rtl Design jobs in Arlington, TX look for?

The top searched job categories for Remote Rtl Design jobs in Arlington, TX are:

What cities near Arlington, TX are hiring for Remote Rtl Design jobs?

Cities near Arlington, TX with the most Remote Rtl Design job openings:

Remote Rtl Design jobs near you
Infographic showing various Remote Rtl Design job openings in Arlington, TX as of June 2026, with employment types broken down into 83% Full Time, and 17% Contract. Highlights an 100% Remote job distribution, with an average salary of $125,423 per year, or $60.3 per hour.

ASIC Engineer - Remote

Purple Hires Inc

Plano, TX • Remote

Contractor

Posted 21 days ago

Job description

Job Description
Key skills for Lead ASIC DFT:
 
please see these key words of in the project description for the profile consideration.
  “SCAN, ATPG, MBIST, Timing Simulations,  SDF, SDC ,  PSV, Diagnosys ,  Pattern Retargeting , Pattern porting,  DRCs,  TetraMax, DFTMax “
Experience
10+ years of hands-on experience in ASIC Design-for-Test (DFT)
Role Summary
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.