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Remote Cpu Design Jobs in California (NOW HIRING)

Tenstorrent

Fabric SOC Architect

Santa Clara, CA · Remote

$100K - $500K/yr

... CPU design, cache coherency protocols, and interconnect fabrics to shape the future of high ... This role is remote, based out of The United States. We welcome candidates at various experience ...

Cornelis Networks

PCIe ASIC Design Engineer

San Jose, CA · On-site +1

... CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI ... This is a remote position for employees residing within the United States. We offer a competitive ...

Tenstorrent

Chiplet Design Architect

Santa Clara, CA · On-site +1

$100K - $500K/yr

As a CPU Chiplet Architect at Tenstorrent, you will define the architecture for next-generation ... This role is remote, based out of The United States. We welcome candidates at various experience ...

Tenstorrent

DFT Engineer

Santa Clara, CA · On-site +1

$100K - $500K/yr

In this role, you will be responsible for DFT implementation using industry standard tools for high-speed CPU core design. This role is remote based out of the United States. We welcome candidates at ...

Hudson Manpower

Senior Infrastructure PM

San Jose, CA · On-site +1

$45/hr

Remote Payrate : $45/hr on W2. As a Project Management team member, the Infrastructure PM will ... OS 10, 4 GB (8 GB+ preferred) RAM, 2 GHz CPU o Mac: OS 10.14+, 4 GB (8 GB+ preferred) RAM, Intel ...

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Infographic showing various Remote Cpu Design job openings in California as of July 2026, with employment types broken down into 17% As Needed, 74% Full Time, 4% Part Time, 4% Contract, and 1% Summer. Highlights an 89% Physical, 5% Hybrid, and 6% Remote job distribution.

RISC-V CPU Microarchitecture / RTL

Tenstorrent

Santa Clara, CA • On-site, Remote

$100K - $500K/yr

Full-time

Posted 18 days ago

Key responsibilities

  • Define and develop microarchitecture specifications for the RISC-V CPU unit, including analysis for verification and PPA closure.

  • Responsible for RTL design, review, refinement, and verification to ensure quality and optimization for power, performance, and area.

  • Use AI tools to assist in CPU design processes and potentially mentor junior engineers based on experience level.

Job description

RISC-V CPU RTL owner will play a key role in developing next-generation CPU design. This position requires a deep understanding of CPU design including Architecture, RTL, Design Verification, Physical Design Flow. The ideal candidate will drive the unit specification, RTL design, and unit verification.

This role is Remote, based out of The United States or Spain.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Key Responsibilities:

  • RISC-V CPU Unit Microarchitecture Specification: Define and develop microarchitecture specifications for the assigned unit (branch predictor, rename, instruction scheduling, vector execution, load/store, vector load/store support). The specification includes not only design, but also comprehensive analysis / strategy for verification and PPA (power, performance, area) closure.
  • RISC-V CPU Core Unit RTL Design: The candidate will be responsible for the quality of RTL including design verification and PPA closure. This includes writing RTL, reviewing / refining unit verification environment, applying right RTL optimization to control PPA.
  • AI Assisted Design Adaption: To maximize the team's output, the candidate actively uses AI tools to accelerate the CPU design process.
  • Mentoring Junior Engineers: depending on a seniority of the engineer, the engineer may mentor junior members in the team.

Qualifications:

  • Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Proven track record of designing high-performance CPU RTL for x86, Arm, POWER, SPARC, or RISC-V.
  • Deep understanding of design verification strategy and trade-offs for verification methodology (simulation, formal, various checkers, etc...)
  • Deep understanding of CPU microarchitecture and PPA trade-off.
  • Basic understanding of RISC-V Architecture including V-extension is preferred.
  • Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog or VHDL.
  • Excellent problem-solving abilities and analytical skills.
  • Strong communication skills, with the ability to convey complex technical concepts to diverse audiences.
  • Ability to work collaboratively in a team-oriented environment and across multiple disciplines.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

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