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Remote Computer Chip Engineer Jobs in Sunnyvale, CA

Tensordyne

Principal ASIC Architect

Sunnyvale, CA · On-site +1

Headquartered in Sunnyvale, CA, and Munich, Germany, with remote team members across North America ... An MS or PhD in Electrical Engineering, Computer Engineering or related engineering discipline. For ...

YO AI Labs

Autodesk Fusion 360 Expert - Remote

San Jose, CA · On-site +1

$40 - $120/hr

Remote Job Overview We are seeking experienced Autodesk Fusion 360 Specialists to contribute their ... No prior AI experience is required--your engineering and CAD expertise are what matter most. Key ...

YO AI Labs

Autodesk Inventor Expert - Remote

San Jose, CA · On-site +1

$30 - $120/hr

Remote Job Overview We are seeking experienced Autodesk Inventor Specialists to contribute their ... No prior AI experience is required--your engineering and CAD expertise are what matter most. Key ...

YO AI Labs

Autodesk Inventor Expert - Remote

Palo Alto, CA · On-site +1

$30 - $120/hr

Remote Job Overview We are seeking experienced Autodesk Inventor Specialists to contribute their ... No prior AI experience is required--your engineering and CAD expertise are what matter most. Key ...

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Remote Computer Chip Engineer information

See Sunnyvale, CA salary details

$56.9K

$142.6K

$161.4K

How much do remote computer chip engineer jobs pay per year?

As of Sep 7, 2026, the average yearly pay for remote computer chip engineer in Sunnyvale, CA is $142,617.00, according to ZipRecruiter salary data. Most workers in this role earn between $130,900.00 and $154,300.00 per year, depending on experience, location, and employer.

What does a remote computer chip engineer do?

A Remote Computer Chip Engineer designs, develops, tests, and optimizes microchips and integrated circuits while working from a remote location. They use specialized software tools to create blueprints, simulate chip behavior, and collaborate with other engineers online. Their work is crucial in developing faster, more efficient processors and electronic devices. By working remotely, they leverage digital communication and project management tools to coordinate with teams around the world.

What are the key skills and qualifications needed to thrive as a remote computer chip engineer, and why are they important?

To thrive as a Remote Computer Chip Engineer, you need a strong background in electrical engineering, digital/analog circuit design, and semiconductor fundamentals, typically supported by a relevant degree. Familiarity with CAD tools like Cadence or Synopsys, experience with HDL languages (such as Verilog or VHDL), and knowledge of simulation and verification systems are essential. Excellent problem-solving, self-motivation, and effective remote communication skills set top engineers apart in virtual teams. These competencies ensure high-quality chip development, efficient collaboration, and successful project delivery in a remote work environment.

What are some common challenges faced by remote computer chip engineers, and how can they be addressed?

Remote Computer Chip Engineers often face challenges related to effective collaboration, particularly when working across different time zones or with team members in various locations. Communication about design updates, debugging, and hardware testing can require extra coordination. To address these issues, teams typically use robust project management tools, regular video meetings, and clear documentation practices. Establishing strong communication channels and proactively sharing progress help ensure everyone stays aligned and projects move forward efficiently.

What are popular job titles related to Remote Computer Chip Engineer jobs in Sunnyvale, CA?

For Remote Computer Chip Engineer jobs in Sunnyvale, CA, the most frequently searched job titles are:

What cities near Sunnyvale, CA are hiring for Remote Computer Chip Engineer jobs?

Cities near Sunnyvale, CA with the most Remote Computer Chip Engineer job openings:

Remote Computer Chip Engineer jobs near you

Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)

Tenstorrent

Santa Clara, CA • Remote

$100K - $500K/yr

Full-time

Posted 18 days ago

Job description

Tenstorrent is seeking  a highly skilled Physical Design Engineer to drive the critical Die-to-Die (D2D) Physical Implementation from RTL to GDSII. This role demands deep expertise in full physical design flow with a specific focus on closing high-speed D2D interfaces for multi-die/chiplet architectures.

This role is remote role open to any location in the U.S.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

  • A seasoned ASIC Physical Design Engineer with 5+ years at advanced nodes (7nm or below) and multiple successful tapeouts.
  • Strong in full-chip implementation, comfortable owning blocks from RTL to GDSII across synthesis, floorplanning, place-and-route, CTS, and sign-off.
  • Deeply familiar with high-speed interfaces (D2D, PCIe, HBM, SerDes) and the physical challenges that come with them (timing, signal integrity, power integrity).
  • Detail-oriented and methodical with STA, constraints, and closure for complex, high-speed designs.
  • A hands-on problem solver who enjoys collaborating across analog, digital, and full-chip teams to debug tough issues.

What We Need

  • Lead Die-to-Die (D2D) physical implementation and closure, taking high-speed D2D PHYs/controllers from netlist to tapeout.
  • Own the full PD flow (RTL-to-GDSII): synthesis, floorplanning, P&R, CTS, optimization, and sign-off.
  • Drive timing and verification, including full STA (setup/hold), SI analysis (crosstalk, IR drop), and achieving sign-off quality DRC/LVS.
  • Improve and maintain physical design methodologies, flows, and automation scripts (Tcl, Python), with specific focus on D2D routing, power grid design, and timing closure.
  • Partner closely with full-chip/chiplet teams to meet all tapeout requirements and with the analog design team to resolve interface issues (LEF/LIB, constraints, integration/debug).
  • Apply strong EDA tool expertise across Synopsys/Cadence/Mentor for implementation, analysis, and verification.
  • Bring a solid academic foundation: B.S./M.S. in EE/CE or related field.

What You'll Learn

  • How to implement and close cutting-edge D2D interfaces in advanced multi-die/chiplet architectures.
  • Advanced strategies for co-optimizing routing, power grid, and timing for high-speed links across dies.
  • Deeper integration techniques working with analog PHY teams, including model handoff (LEF/LIB) and constraint-driven interface design.
  • How to drive repeatable, scalable PD methodologies for high-speed interfaces that can be leveraged across future chiplets and products.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. 

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