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Remote Asic Verification Manager Jobs (NOW HIRING)

Remote Duration: 3+ months Commitment: 40 hours/week Role Responsibilities * Evaluate digital chip ... Experience with ASIC design flows and common EDA tools . * Ability to write clear design ...

New

$123.20K - $169.80K/yr

The successful candidate will have a background in SOC, ASIC or FPGA development and/or verification, and experience in leading or managing SOC, ASIC or FPGA projects or managing people. Location:

Headquartered in Sunnyvale, CA, and Munich, Germany, with remote team members across North America ... verification teams, SOC physical design teams, interdisciplinary software teams, product management ...

ASIC Digital Design Architect

Austin, TX · On-site +1

$181K - $271K/yr

... 181000-$271000 Remote Eligible No Date Posted 05/11/2026 We Are: At Synopsys, we drive the ... We lead in chip design, verification, and IP integration, empowering the creation of high ...

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Infographic showing various Remote Asic Verification Manager job openings in the United States as of May 2026, with employment types broken down into 97% Full Time, 2% Part Time, and 1% Contract. Highlights an 98% Physical, and 2% Hybrid job distribution.

Design Verification Engineer

Mercor

San Jose, CA • Remote

$100 - $175/hr

Full-time

Posted 21 hours ago


Job description

About the job

Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam D'Angelo, Larry Summers, and Jack Dorsey.

Position: RTL Design Engineers
Type: Contract
Compensation: $100–$175/hour
Location: Remote
Duration: 3+ months
Commitment: 40 hours/week

Role Responsibilities

  • Evaluate digital chip design workflows to enhance AI model training and evaluation.
  • Design and verify RTL components using Verilog/SystemVerilog.
  • Collaborate with architecture, verification, and implementation teams to improve model outputs.
  • Develop reusable verification components and testbench infrastructure.
  • Leverage LLM-based tools to accelerate chip design and verification processes.
  • Work independently and asynchronously to meet project deadlines.

Qualifications

Must-Have

  • 3–10 years of experience in digital RTL design or design verification.
  • Strong proficiency in Verilog/SystemVerilog and UVM.
  • Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols.
  • Experience with ASIC design flows and common EDA tools.
  • Ability to write clear design documentation and communicate technical tradeoffs.

Preferred

  • Knowledge of AMBA protocols (AXI, AHB, APB).
  • Background in CPU, GPU/ML accelerator, networking, memory subsystem, PCIe/high-speed IO, SoC interconnect, low-power design.
  • Exposure to formal verification or SV/UVM-based design verification.

Start Date

  • Week of 04/23; applications reviewed on a rolling basis.

Compensation & Legal

  • Hourly contractor, Paid weekly.

Application Process (Takes 20–30 mins to complete)

  • Upload resume
  • AI interview based on your resume
  • Submit form

Resources & Support

  • For details about the interview process and platform information, please check: https://talent.docs.mercor.com/welcome
  • For any help or support, reach out to: support@mercor.com

PS: Our team reviews applications daily. Please complete your AI interview and application steps to be considered for this opportunity.


#hiringmercor