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How much do pll analog mixed signal design engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for pll analog mixed signal design engineer in the United States is $186,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $202,000.00 and $202,000.00 per year, depending on experience, location, and employer.

What does a PLL Analog Mixed Signal Design Engineer do?

A PLL (Phase-Locked Loop) Analog Mixed Signal Design Engineer specializes in designing and developing integrated circuits that combine both analog and digital components, with a focus on PLL circuits. These engineers work on the architecture, simulation, layout, and testing of PLLs for applications such as communication systems, clock generation, and data converters. Their responsibilities include ensuring that circuits meet performance specifications, collaborating with cross-functional teams, and troubleshooting any issues that arise during the design and verification phases. They need a strong background in electronics, signal processing, and semiconductor technology.

What are the key skills and qualifications needed to thrive as a PLL Analog Mixed Signal Design Engineer?

To thrive as a PLL Analog Mixed Signal Design Engineer, you need a strong background in analog and digital circuit design, semiconductor physics, and typically a degree in electrical or electronics engineering. Familiarity with EDA tools like Cadence, SPICE simulators, and understanding of industry standards for IC design are crucial, along with knowledge of PLL architecture and verification methodologies. Strong problem-solving skills, attention to detail, and effective communication are vital soft skills for collaborating with cross-functional teams and troubleshooting complex issues. These skills ensure the development of reliable, high-performance circuits that meet specifications and project timelines in the demanding field of IC design.

What are some common challenges faced by PLL Analog Mixed Signal Design Engineers during the development cycle?

PLL Analog Mixed Signal Design Engineers frequently encounter challenges such as managing noise and jitter, achieving low power consumption, and ensuring robust performance across process, voltage, and temperature variations. Coordinating closely with digital and layout teams is often necessary to ensure that the mixed-signal blocks integrate seamlessly with the rest of the chip. Additionally, debugging and validating PLL performance in silicon can be complex, requiring deep understanding of both analog circuitry and digital verification methods.

What are popular job titles related to Pll Analog Mixed Signal Design Engineer jobs?

For Pll Analog Mixed Signal Design Engineer jobs, the most frequently searched job titles are:

Infographic showing various Pll Analog Mixed Signal Design Engineer job openings in the United States as of August 2026, with employment types broken down into 88% Full Time, 7% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $186,238 per year, or $89.5 per hour.

Principal PLL Design Engineer

Irvine, CA • On-site

Celero Communications, Inc.
See more jobs at Celero Communications, Inc.external

$150K - $250K/yr

Full-time

Re-posted 28 days ago

Job description

Are you a PLL Design Engineer passionate about developing the high-speed clocking technology that will power the next generation of AI infrastructure? Join our fast-growing semiconductor startup and help deliver disruptive High-Speed Interconnect solutions for tomorrow's optical networks.
We are seeking a High-Speed CMOS PLL Analog Design Engineer to play a key role in the architecture and design of advanced clocking circuits for next-generation optical transceivers, high-speed SerDes, and high-performance ADC/DAC systems. In this role, you will architect and design state-of-the-art PLLs for industry-leading transceivers, working alongside a world-class team to solve some of the most challenging mixed-signal design problems in advanced CMOS technologies. This is an opportunity to make a significant technical impact while helping build groundbreaking products from the ground up.
Locations: Irvine, CA (HQ) | San Jose, CA | Vancouver, BC | Ottawa, ON
What You Will Do:
• Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range
• Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre
• Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization
• Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies
• Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment
• Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies
What You Will Bring:
• Master's degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs
• Proficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling
• Strong communication and documentation skills
Annual Base Salary Range for US: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

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