Develop P‑cells, scripts, and automation for physical design, verification, optimization, and ... VLSI, or a related semiconductor engineering role * Experience programming in SKILL/Skill ...
Develop P‑cells, scripts, and automation for physical design, verification, optimization, and ... VLSI, or a related semiconductor engineering role * Experience programming in SKILL/Skill ...
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Santa Clara, CA · Hybrid
$159K - $164K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Santa Clara, CA · Hybrid
$159K - $164K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Austin, TX · Hybrid
$134K - $138K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Austin, TX · Hybrid
$134K - $138K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Physical Design Engineer * Design Verification Engineer Compensation up to $225K DOE + strong benefits + long-term project stability. What You Need (All Roles) * 8+ years of pre-silicon ASIC / VLSI ...
Quick apply
Physical Design Engineer * Design Verification Engineer Compensation up to $225K DOE + strong benefits + long-term project stability. What You Need (All Roles) * 8+ years of pre-silicon ASIC / VLSI ...
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Austin, TX · Hybrid
$134K - $138K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Austin, TX · Hybrid
$134K - $138K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Santa Clara, CA · Hybrid
$159K - $164K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Santa Clara, CA · Hybrid
$159K - $164K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Austin, TX · On-site
$134K - $138K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Austin, TX · On-site
$134K - $138K/yr
We are seeking a R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS (10+ Yrs)
Folsom, CA · On-site
$145K - $149K/yr
VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS Folsom, CA 3 + Months Role: Lead block-level physical design from RTL to GDSII. Must Have: 10+ years exp, advanced nodes, and Fusion Compiler.
New
VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS (10+ Yrs)
Folsom, CA · On-site
$145K - $149K/yr
VLSI Physical Design Engineer - ASIC/SoC - RTL to GDS Folsom, CA 3 + Months Role: Lead block-level physical design from RTL to GDSII. Must Have: 10+ years exp, advanced nodes, and Fusion Compiler.
New
Physical Design Engineer
Sunnyvale, CA · On-site
$159K - $164K/yr
Job Title: Physical Design Engineer Location:Sunnyvale, CA OR Austin,TX Duration: Long term ... The ideal candidate will be responsible for various aspects of the backend VLSI design flow ...
Quick apply
Physical Design Engineer
Sunnyvale, CA · On-site
$159K - $164K/yr
Job Title: Physical Design Engineer Location:Sunnyvale, CA OR Austin,TX Duration: Long term ... The ideal candidate will be responsible for various aspects of the backend VLSI design flow ...
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Physical Design Engineer
San Jose, CA · On-site
$159K - $164K/yr
Company Description Insilico is an End-to-End specialized VLSI, Embedded Design & Software services ... Job Title: Physical Design Engineer Location: San Jose, CA Experience: 5- 8 Years Duration: 12 ...
Physical Design Engineer
San Jose, CA · On-site
$159K - $164K/yr
Company Description Insilico is an End-to-End specialized VLSI, Embedded Design & Software services ... Job Title: Physical Design Engineer Location: San Jose, CA Experience: 5- 8 Years Duration: 12 ...
We are looking for an experienced VLSI physical design engineer to join this innovative team as a technical expert. The candidate will be a key contributor and leader for AMD's next generation cores ...
We are looking for an experienced VLSI physical design engineer to join this innovative team as a technical expert. The candidate will be a key contributor and leader for AMD's next generation cores ...
Physical Design Engineer
San Jose, CA · On-site
$159K - $164K/yr
Company Description Insilico is an End-to-End specialized VLSI, Embedded Design & Software services ... Job Title: Physical Design Engineer Location: San Jose, CA Experience: 5- 8 Years Duration: 12 ...
Physical Design Engineer
San Jose, CA · On-site
$159K - $164K/yr
Company Description Insilico is an End-to-End specialized VLSI, Embedded Design & Software services ... Job Title: Physical Design Engineer Location: San Jose, CA Experience: 5- 8 Years Duration: 12 ...
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
$140K - $156K/yr
The Physical Design Engineer willbe an integral part of the physical design team with all aspects ... Good understanding in VLSI digital design/Layout/Timing closure * Basic knowledge on circuit design ...
$140K - $156K/yr
The Physical Design Engineer willbe an integral part of the physical design team with all aspects ... Good understanding in VLSI digital design/Layout/Timing closure * Basic knowledge on circuit design ...
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
We are seeking a Senior R&D Software Engineer with proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.
Senior Microprocessor VLSI Physical Design Engineer
Fort Collins, CO · On-site
$156K/yr
We are looking for an experienced VLSI physical design engineer to join this innovative team as a technical expert. The candidate will be a key contributor and leader for AMD's next generation cores ...
Senior Microprocessor VLSI Physical Design Engineer
Fort Collins, CO · On-site
$156K/yr
We are looking for an experienced VLSI physical design engineer to join this innovative team as a technical expert. The candidate will be a key contributor and leader for AMD's next generation cores ...
VLSI: Research creative and innovative ASIC and VLSI design techniques and/or novel digital VLSI circuits. Apply machine learning, generative AI, and innovative tools and methodologies to automated ...
VLSI: Research creative and innovative ASIC and VLSI design techniques and/or novel digital VLSI circuits. Apply machine learning, generative AI, and innovative tools and methodologies to automated ...
Physical Design Vlsi information
See salary details
$95K - $99.2K
0% of jobs
$99.2K - $103.5K
0% of jobs
$103.5K - $107.7K
0% of jobs
$107.7K - $111.9K
0% of jobs
$111.9K - $116.1K
0% of jobs
$116.1K - $120.4K
0% of jobs
$120.4K - $124.6K
0% of jobs
$124.6K - $128.8K
0% of jobs
$128.8K - $133K
1% of jobs
$135.4K is the 25th percentile. Wages below this are outliers.
$133K - $137.3K
43% of jobs
The median wage is $137.7K / yr.
$137.3K - $141.5K
56% of jobs
$95K
$141.5K
How much do physical design vlsi jobs pay per year?
What is the difference between Physical Design Vlsi vs Digital IC Design Engineer?
| Aspect | Physical Design Vlsi | Digital IC Design Engineer |
|---|---|---|
| Primary Focus | Implementing physical layouts, placement, routing of VLSI chips | Designing digital circuits, logic design, HDL coding |
| Skills & Certifications | EDA tools, CMOS fabrication knowledge, scripting skills | HDL languages (Verilog/VHDL), simulation tools, digital design principles |
| Work Environment | Semiconductor fabrication facilities, design labs | Design offices, EDA tool environments |
| Industry Usage | Foundries, chip design companies | Integrated circuit design firms, tech companies |
Physical Design Vlsi specialists focus on the physical implementation of chip layouts, ensuring manufacturability and performance. Digital IC Design Engineers concentrate on creating digital logic circuits and verifying their functionality. Both roles require knowledge of digital design principles, but Physical Design Vlsi emphasizes physical implementation, while Digital IC Design emphasizes circuit design and simulation.

Staff CAD Design Automation Engineer
Boise, ID • On-site
Other
Re-posted 24 days ago
Micron Technology rating
8.6
Based on 43 frontline employees who took The Breakroom Quiz
Job description
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Our EDA and Design Enablement team sits at the heart of Micron’s memory development. We build and support the tools and flows that enable world‑class CMOS design at scale. Working closely with design, layout, and process teams, we thrive on solving hard technical problems that directly impact product success.
As a CAD Engineer, you will play a critical role in keeping our design ecosystem running efficiently and reliably. You’ll develop, improve, and support both in‑house and commercial EDA tools while partnering closely with engineers across the design flow. This is a hands‑on role for someone who enjoys debugging, innovating, and enabling others to do their best work.
Responsibilities- Design, develop, and support CAD software, EDA tools, flows, and methodologies for CMOS design and verification
- Debug, evaluate, and support in‑house and commercial EDA solutions in a production environment
- Develop P‑cells, scripts, and automation for physical design, verification, optimization, and tape‑out
- Collaborate closely with design, PI, and process teams to solve workflow and tool challenges, and to implement scalable layout methodologies aligned with PDK requirements
- Document processes and provide training and support for end users
- Bachelor’s degree in Computer Engineering, Computer Science, or a related field
- 2+ years of experience in CAD, VLSI, or a related semiconductor engineering role
- Experience programming in SKILL/Skill++ (Cadence), Python, and/or Perl
- Experience with PDK development and/or validation and familiarity with Cadence EDA tools and flows
- Experience with Linux/Unix environments, shell scripting, databases, and version control
- Effective communication skills in a collaborative engineering environment
- Understanding of CMOS process fundamentals and layout design rules
- Understanding of photo/metrology marks and layout design
- Prior work supporting or developing EDA design tools, flows, and methodologies
- Experience supporting automation for physical design, verification, or tape‑out flows
CAD Engineer 4
EEO StatementMicron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
What Micron Technology employees say
Pay
Benefits
Hours and flexibility
Workplace
Get the full story on Breakroom
About Micron Technology
Sourced by ZipRecruiter
Industry
Semiconductor and electronic component manufacturing
Company size
10,000+ Employees
Headquarters location
Boise, ID, US
Year founded
2019