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Permanent Ran Optimization Engineer Jobs in Newark, NJ

Airspan

FPGA DESIGN ENGINEER

Warren, NJ · On-site

$127K - $176K/yr

As an FPGA Design Engineer , you will be responsible for designing, implementing, and optimizing FPGA-based solutions for wireless communication applications, including 4G, 5G, and O-RAN systems. You ...

JLL

Building Engineering - Multiple Openings

Edison, NJ · On-site

You will play a crucial role in ensuring optimal comfort, air quality, and energy efficiency for ... engineer, Boiler operators license (CoH boiler operators license) Estimated total compensation ran ...

Fireworks AI

AI Field Engineer - AI Natives

New York, NY · On-site

Frontier RL is cheaper than the mega-cluster narrative suggests: we ran cross-region rollouts using ... Deploy and validate new model families on inference frameworks (vLLM, SGLang), determining optimal ...

AT&T

Sr. Specialist Member of Technical Staff

Middletown, NJ · On-site

$160K - $192K/yr

Apply advanced engineering and scientific knowledge in regard to architecture. Conduct quantitative ... Utilize P1/P2, Open Access, SDN, RAN, and Fiber Broadband. Utilize ServiceNow, GPT4, Python, Java ...

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All JobsPermanent Ran Optimization Engineer JobsPermanent Ran Optimization Engineer Jobs in Newark, NJ

Permanent Ran Optimization Engineer information

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How much do permanent ran optimization engineer jobs pay per hour?

As of Jul 10, 2026, the average hourly pay for permanent ran optimization engineer in Newark, NJ is $62.38, according to ZipRecruiter salary data. Most workers in this role earn between $45.24 and $76.92 per hour, depending on experience, location, and employer.

What is the difference between Permanent Ran Optimization Engineer vs Radio Network Optimization Engineer?

AspectPermanent Ran Optimization EngineerRadio Network Optimization Engineer
CredentialsBachelor's in Telecommunications, Engineering, or related field; certifications like Nokia, Ericsson, or HuaweiBachelor's in Telecommunications, Electrical Engineering, or related; similar certifications
Work EnvironmentTelecom companies, network providers, field and office settingsTelecom companies, network providers, field and office settings
Industry UsageCommonly employed in telecom industry for permanent network optimization rolesUsed interchangeably in telecom for network performance improvement roles

The Permanent Ran Optimization Engineer and Radio Network Optimization Engineer roles are highly similar, often overlapping in credentials, work environment, and industry usage. The main difference lies in terminology preference, with both focusing on optimizing radio access networks to improve coverage and performance. Both roles are essential in telecom network management and require comparable skills and certifications.

What are the key skills and qualifications needed to thrive as a Permanent RAN Optimization Engineer, and why are they important?

To thrive as a Permanent RAN Optimization Engineer, you need a solid background in telecommunications, RF engineering, and cellular network concepts, often supported by a degree in electrical engineering or a related field. Familiarity with network optimization tools (such as TEMS, Atoll, or Actix), drive test software, and relevant industry certifications (like CCNA or 5G certifications) is typically required. Strong analytical thinking, problem-solving abilities, and effective communication skills set top performers apart in this role. These skills and qualifications are crucial for ensuring optimal network performance, efficient troubleshooting, and collaboration across technical teams.

What is a Permanent RAN Optimization Engineer?

A Permanent RAN Optimization Engineer is a telecommunications professional responsible for analyzing and improving the performance of Radio Access Networks (RAN) on a long-term, full-time basis. Their main duties include monitoring network performance, identifying issues, and implementing solutions to optimize signal quality, capacity, and coverage. They work with technologies such as 4G LTE and 5G, using specialized tools to ensure efficient data and voice transmission. These engineers collaborate with other technical teams to enhance user experience and support the rollout of new network features.

How does a Permanent RAN Optimization Engineer typically collaborate with network operations and planning teams?

As a Permanent RAN Optimization Engineer, you’ll regularly collaborate with network operations and planning teams to ensure optimal radio access network (RAN) performance. Your role often involves analyzing network KPIs, sharing insights on coverage or capacity issues, and coordinating technical solutions like parameter tuning or hardware upgrades. Effective communication and cross-functional teamwork are essential, as you'll work together to identify bottlenecks, implement enhancements, and monitor post-optimization results. This collaborative approach helps deliver a high-quality mobile experience for end users.
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Permanent Ran Optimization Engineer jobs near you

FPGA DESIGN ENGINEER

Airspan

Warren, NJ • On-site

$127K - $176K/yr

Full-time

Re-posted 18 hours ago

Job description

Airspan Careers
FPGA DESIGN ENGINEER
Location: Warren, New Jersey or Plano, TX, Remote possible if perfect fit and live in another location
Company: AirSpan Networks
About AirSpan
AirSpan Networks is a global provider of innovative 4G and 5G network solutions, enabling efficient and cost-effective connectivity for operators, enterprises, and industrial applications. We are seeking an experienced FPGA Design Engineer to contribute to the development of cutting-edge wireless communication systems.
Job Description
As an FPGA Design Engineer, you will be responsible for designing, implementing, and optimizing FPGA-based solutions for wireless communication applications, including 4G, 5G, and O-RAN systems. You will work closely with system architects, software engineers, and verification engineers to develop high-performance digital hardware solutions.
Key Responsibilities:
  • Design and implement FPGA-based digital signal processing (DSP) and communication systems.
  • Develop RTL designs in Verilog/System Verilog, ensuring efficient and high-performance implementations.
  • Integrate and optimize FPGA-based modules for wireless technologies, including 4G, 5G, and O-RAN architectures.
  • Perform FPGA synthesis, timing analysis, and resource utilization optimization.
  • Collaborate with verification engineers to define test benches and validate designs.
  • Debug and troubleshoot FPGA-based systems using simulation tools and hardware debugging techniques.
  • Work with C/C++ and Python for algorithm modeling and hardware/software co-design.
  • Implement high-speed interfaces such as PCIe, Ethernet, and JESD204B.
  • Document design specifications, test results, and technical reports.

Qualifications & Experience:
Critical Skills: O-RAN, DSP, Xilinx FPGA, RF-SOC, PTP, Ethernet
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 10 years of experience in FPGA design and development.
  • Proficiency in Verilog/SystemVerilog for digital logic design.
  • Experience with FPGA development tools such as Xilinx Vivado, Intel Quartus
  • Knowledge of wireless communication systems, 4G/5G networks, and O-RAN architectures.
  • Knowledgeable with PTP protocol IEEE1588 (PTPv2)).
  • Strong understanding of DSP algorithms and their FPGA implementations.
  • Experience in debugging in the lab using Vivado ILAs and Experience using Signal Generators and analyzers
  • Familiarity with high-speed communication protocols (PCIe, Ethernet, JESD204B, CPRI, etc.).
  • Experience with C/C++ and Python for hardware modeling and testing.
  • Strong problem-solving and analytical skills with a proactive approach to debugging complex systems.

Preferred Skills:
  • Experience with FPGA-based acceleration for AI/ML applications.
  • Understanding of MATLAB/Simulink for DSP algorithm verification.
  • Knowledge of power optimization techniques for FPGA designs.
  • Experience with Linux device drivers and embedded systems.

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