NPU Architecture & Dataflow: Define and own the end-to-end NPU micro-architecture, including high-throughput tensor/matrix engines, vector units, and specialized activation functional units.
NPU Architecture & Dataflow: Define and own the end-to-end NPU micro-architecture, including high-throughput tensor/matrix engines, vector units, and specialized activation functional units.
NPU Architecture & Dataflow: Define and own the end-to-end NPU micro-architecture, including high-throughput tensor/matrix engines, vector units, and specialized activation functional units.
NPU Architecture & Dataflow: Define and own the end-to-end NPU micro-architecture, including high-throughput tensor/matrix engines, vector units, and specialized activation functional units.
Principal Gpu/Npu Ai System Architect
Austin, TX · On-site
$180 - $260/hr
GPU / NPU Architecture & HW‑SW Co‑Design * Develop deep architectural understanding of GPU, NPU, and heterogeneous SoC designs, including memory hierarchies, interconnects, scheduling, and power ...
Principal Gpu/Npu Ai System Architect
Austin, TX · On-site
$180 - $260/hr
GPU / NPU Architecture & HW‑SW Co‑Design * Develop deep architectural understanding of GPU, NPU, and heterogeneous SoC designs, including memory hierarchies, interconnects, scheduling, and power ...
GPU / NPU Architecture & HW-SW Co - Design * Develop deep architectural understanding of GPU, NPU, and heterogeneous SoC designs , including memory hierarchies, interconnects, scheduling, and power ...
GPU / NPU Architecture & HW-SW Co - Design * Develop deep architectural understanding of GPU, NPU, and heterogeneous SoC designs , including memory hierarchies, interconnects, scheduling, and power ...
GPU / NPU Architecture & HW-SW Co Design * Develop deep architectural understanding of GPU, NPU, and heterogeneous SoC designs , including memory hierarchies, interconnects, scheduling, and power ...
GPU / NPU Architecture & HW-SW Co Design * Develop deep architectural understanding of GPU, NPU, and heterogeneous SoC designs , including memory hierarchies, interconnects, scheduling, and power ...
GPU Driver & Memory Management Architect
Spring, TX · On-site
$147K - $230K/yr
The role will deliver improved GPU/NPU utilization for AI workloads. The role offers tangible feedback to enhance product quality, while overseeing tracking and reporting of product-related ...
GPU Driver & Memory Management Architect
Spring, TX · On-site
$147K - $230K/yr
The role will deliver improved GPU/NPU utilization for AI workloads. The role offers tangible feedback to enhance product quality, while overseeing tracking and reporting of product-related ...
GPU Driver & Memory Management Architect
Spring, TX · On-site
$147K - $230K/yr
The role will deliver improved GPU/NPU utilization for AI workloads. The role offers tangible feedback to enhance product quality, while overseeing tracking and reporting of product-related ...
GPU Driver & Memory Management Architect
Spring, TX · On-site
$147K - $230K/yr
The role will deliver improved GPU/NPU utilization for AI workloads. The role offers tangible feedback to enhance product quality, while overseeing tracking and reporting of product-related ...
Pre‑Silicon Power Modeling Leader - x86 SoCs
Austin, TX · On-site
$156K/yr
Deep knowledge of x86 micro-architecture (CPU pipelines, caches), GPU/NPU basics, memory subsystems, interconnect/fabric behavior, and power delivery/PDN interactions. * Proven ability to define DVFS ...
Pre‑Silicon Power Modeling Leader - x86 SoCs
Austin, TX · On-site
$156K/yr
Deep knowledge of x86 micro-architecture (CPU pipelines, caches), GPU/NPU basics, memory subsystems, interconnect/fabric behavior, and power delivery/PDN interactions. * Proven ability to define DVFS ...
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127.20 - $190.80/hr
Overview Qualcomm Technologies, Inc. is seeking a design-focused engineer to contribute to the next generation of microarchitecture and logic for the Hexagon NPU, supporting a wide range of AI/ML ...
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127.20 - $190.80/hr
Overview Qualcomm Technologies, Inc. is seeking a design-focused engineer to contribute to the next generation of microarchitecture and logic for the Hexagon NPU, supporting a wide range of AI/ML ...
Deep knowledge of x86 microarchitecture (CPU pipelines, caches), GPU/NPU basics, memory subsystems, interconnect/fabric behavior, and power delivery/PDN interactions. * Proven ability to define DVFS ...
Deep knowledge of x86 microarchitecture (CPU pipelines, caches), GPU/NPU basics, memory subsystems, interconnect/fabric behavior, and power delivery/PDN interactions. * Proven ability to define DVFS ...
Implement and optimize ML operator kernels and embedded libraries for on-chip acceleration (DSP, vector, NPU), including HeliaDSP and HeliaCore components. * Build and maintain on-device profiling ...
Implement and optimize ML operator kernels and embedded libraries for on-chip acceleration (DSP, vector, NPU), including HeliaDSP and HeliaCore components. * Build and maintain on-device profiling ...
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127K - $190K/yr
Design and development of next-generation microarchitecture and logic for Qualcomm's state-of-the-art Hexagon NPU, powering a wide range of AI/ML applications. In addition to microarchitecture and ...
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127K - $190K/yr
Design and development of next-generation microarchitecture and logic for Qualcomm's state-of-the-art Hexagon NPU, powering a wide range of AI/ML applications. In addition to microarchitecture and ...
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127K - $190K/yr
Design and development of next-generation microarchitecture and logic for Qualcomm's state-of-the-art Hexagon NPU, powering a wide range of AI/ML applications. In addition to microarchitecture and ...
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127K - $190K/yr
Design and development of next-generation microarchitecture and logic for Qualcomm's state-of-the-art Hexagon NPU, powering a wide range of AI/ML applications. In addition to microarchitecture and ...
Implement and optimize ML operator kernels and embedded libraries for on-chip acceleration (DSP, vector, NPU), including HeliaDSP and HeliaCore components. * Build and maintain on-device profiling ...
Implement and optimize ML operator kernels and embedded libraries for on-chip acceleration (DSP, vector, NPU), including HeliaDSP and HeliaCore components. * Build and maintain on-device profiling ...
Implement and optimize ML operator kernels and embedded libraries for on-chip acceleration (DSP, vector, NPU), including HeliaDSP and HeliaCore components. * Build and maintain on-device profiling ...
Implement and optimize ML operator kernels and embedded libraries for on-chip acceleration (DSP, vector, NPU), including HeliaDSP and HeliaCore components. * Build and maintain on-device profiling ...
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127K - $190K/yr
Design and development of next‑generation microarchitecture and logic for Qualcomm's state‑of‑the‑art Hexagon NPU, powering a wide range of AI/ML applications. In addition to ...
AI/ML Logic Design Engineer-Senior
Austin, TX · On-site
$127K - $190K/yr
Design and development of next‑generation microarchitecture and logic for Qualcomm's state‑of‑the‑art Hexagon NPU, powering a wide range of AI/ML applications. In addition to ...
Principal Performance Architect
Austin, TX · On-site
$175K/yr
Lead pre-silicon performance architecture , including workload-driven performance projections across CPU, GPU, NPU, memory, interconnect, and I/O subsystems. * Build and refine cycle-accurate, trace ...
Principal Performance Architect
Austin, TX · On-site
$175K/yr
Lead pre-silicon performance architecture , including workload-driven performance projections across CPU, GPU, NPU, memory, interconnect, and I/O subsystems. * Build and refine cycle-accurate, trace ...
Provide customer and market feedback to help guide future microprocessor, microcontroller, NPU, software, and solution roadmaps. Job Responsibility: * Develop and execute global segment strategies ...
Provide customer and market feedback to help guide future microprocessor, microcontroller, NPU, software, and solution roadmaps. Job Responsibility: * Develop and execute global segment strategies ...
Npu information
See Texas salary details
$10.53 - $13.44
12% of jobs
$13.44 - $16.35
12% of jobs
$17.20 is the 25th percentile. Wages below this are outliers.
$16.35 - $19.26
6% of jobs
$19.26 - $22.17
0% of jobs
$22.17 - $25.08
17% of jobs
The median wage is $25.38 / hr.
$25.08 - $27.99
36% of jobs
$27.99 - $30.91
1% of jobs
$30.91 - $33.82
0% of jobs
$33.82 - $36.73
8% of jobs
$36.73 - $39.64
5% of jobs
$39.64 - $42.55
3% of jobs
$10
$25
$42
How much do npu jobs pay per hour?
What is an NPU?
What are the key skills and qualifications needed to thrive as an NPU engineer, and why are they important?
How does an NPU engineer typically collaborate with software development teams during product development?
What is the difference between Npu vs Network Planning Engineer?
| Aspect | Npu | Network Planning Engineer |
|---|---|---|
| Required Credentials | Typically a degree in telecommunications, electronics, or related field; certifications like CCNA or CCNP | Similar degrees; certifications like CCNA, CCNP, or equivalent |
| Work Environment | Telecom companies, network providers, data centers | Telecom firms, ISPs, network service providers |
| Employer & Industry Usage | Designs and manages network hardware and infrastructure | Plans, designs, and optimizes network layouts and capacity |
Both roles require similar technical credentials and work in the telecommunications industry. While Npu focuses more on hardware and network infrastructure management, Network Planning Engineers concentrate on designing and optimizing network layouts. They often collaborate but serve different functions within network development and maintenance.
What are popular job titles related to Npu jobs in Texas?
For Npu jobs in Texas, the most frequently searched job titles are:
What job categories do people searching Npu jobs in Texas look for?
The top searched job categories for Npu jobs in Texas are:

Full-time
Re-posted 10 days ago
Job description
We are looking for a Principal NPU Hardware Architect with 10 to 15 years of experience to drive the architectural definition and hardware implementation of high-performance Neural Processing Units (NPUs) targeted for microcontrollers and microprocessors addressing Automotive high performance compute. This is a hardware-oriented role that requires a deep understanding of the full silicon lifecycle, combined with a strong background in hardware-software co-design to ensure the NPU architecture is highly optimized for compiler-driven execution and software stacks.
Responsibilities:
- NPU Architecture & Dataflow: Define and own the end-to-end NPU micro-architecture, including high-throughput tensor/matrix engines, vector units, and specialized activation functional units.
- Hardware-Software Co-Design: Partner closely with compiler and software teams to define instruction sets (ISA), memory management schemes, and hardware-aware graph optimizations.
- Virtualization & Multi-Tenancy: Architect hardware-assisted virtualization features to enable secure resource sharing and multi-tenant execution in cloud or edge environments.
- Interconnect & Fabric: Design and integrate high-bandwidth Bus fabrics (e.g., NoC, CHI) and DMA controllers optimized for the massive data movement inherent in AI workloads.
- Infrastructure & Power: Lead the definition of SoC infrastructure elements, including complex clock/reset domains and advanced power management strategies to maximize performance-per-watt.
- Performance Modeling: Develop bit-accurate and cycle-accurate C++/SystemC models to validate architectural choices and enable early software development.
- Full Design Flow: Oversee the transition from architectural spec to RTL, providing technical leadership through verification, physical design, and post-silicon bring-up.
- Education: Bachelor's or Master's in Electrical Engineering or Computer Engineering (PhD desirable)
- Experience: 12+ years in AI accelerator, NPU, or GPU hardware architecture and RTL design.
- Domain Expertise: Deep knowledge of deep learning primitives (CNNs, Transformers, RNNs) and how they map to spatial compute hardware.
- Software Awareness: Strong understanding of compiler backends (e.g., LLVM, MLIR), IR transformations, and how hardware features like scratchpad memories or tiling impact compiler efficiency.
- System Integration: Proven track record with modern SoC protocols (AXI/ACE/CHI) and integrating NPU cores into larger system-on-chip environments.
- Modeling Skills: Expert-level proficiency in SystemC/TLM or C++ for architectural performance modeling and hardware-software co-verification.
- Leadership: Ability to act as a technical authority, mentoring junior designers and influencing cross-functional roadmaps.
Renesas is an embedded semiconductor solution provider driven by its Purpose 'To Make Our Lives Easier.' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.
With a diverse team of over 22,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, 'To Make Our Lives Easier.'
At Renesas, you can:
- Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.
- Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people's lives easier, safe and secure.
- Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.
Are you ready to own your success and make your mark?
Join Renesas. Shape Your Future with Us.
Renesas Electronics is an equal opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law. For more information, please read our Diversity & Inclusion Statement.
Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.
We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.